| 2006 |
|---|
| 5 | EE | Tomasz Madajczak,
Henryk Krawczyk:
Integrating SHECS-Based Critical Sections with Hardware SMP Scheduler in TLP-CMPs.
PARELEC 2006: 62-67 |
| 2005 |
|---|
| 4 | | Tomasz Madajczak,
Henryk Krawczyk:
Implementing Critical Sections with the Shared Explicit Cache System in the Shared Memory Parallel Architectures.
PARCO 2005: 699-706 |
| 3 | EE | Tomasz Madajczak:
Taking Advantage of the SHECS-Based Critical Sections in the Shared Memory Parallel Architectures.
PPAM 2005: 26-33 |
| 2004 |
|---|
| 2 | EE | Henryk Krawczyk,
Tomasz Madajczak:
Optimal Programming of Critical Sections in Modern Network Processors under Performance Requirements.
PARELEC 2004: 25-30 |
| 1 | EE | Tomasz Madajczak:
An Optimal Abstraction Model for Hardware Multithreading in Modern Processor Architectures.
PARELEC 2004: 71-76 |
