Hanpei Koike

2008
23	EE	Shin-ichi O'Uchi, Meishoku Masahara, Kazuhiko Endo, Yongxun Liu, Takashi Matsukawa, Kunihiro Sakamoto, Toshihiro Sekigawa, Hanpei Koike, Eiichi Suzuki: FinFET-Based Flex-Vth SRAM Design for Drastic Standby-Leakage-Current Reduction. IEICE Transactions 91-C(4): 534-542 (2008)
22	EE	Yohei Matsumoto, Masakazu Hioki, Takashi Kawanami, Hanpei Koike, Toshiyuki Tsutsumi, Tadashi Nakagawa, Toshihiro Sekigawa: Suppression of Intrinsic Delay Variation in FPGAs using Multiple Configurations. TRETS 1(1): (2008)
2007
21	EE	Yohei Matsumoto, Masakazu Hioki, Takashi Kawanami, Toshiyuki Tsutsumi, Tadashi Nakagawa, Toshihiro Sekigawa, Hanpei Koike: Performance and yield enhancement of FPGAs with within-die variation using multiple configurations. FPGA 2007: 169-177
20	EE	Takashi Kawanami, Masakazu Hioki, Yohei Matsumoto, Toshiyuki Tsutsumi, Tadashi Nakagawa, Toshihiro Sekigawa, Hanpei Koike: Optimization of the Body Bias Voltage Set (BBVS) for Flex Power FPGA. IEICE Transactions 90-D(12): 1947-1955 (2007)
2006
19	EE	Masakazu Hioki, Takashi Kawanami, Toshiyuki Tsutsumi, Tadashi Nakagawa, Toshihiro Sekigawa, Hanpei Koike: Evaluation of granularity on threshold voltage control in flex power FPGA. FPGA 2006: 223
18	EE	Yohei Matsumoto, Hanpei Koike, Akira Masaki: FPGAs with multidimensional mesh topology. FPGA 2006: 223
2004
17	EE	Takashi Kawanami, Masakazu Hioki, Hiroshi Nagase, Toshiyuki Tsutsumi, Tadashi Nakagawa, Toshihiro Sekigawa, Hanpei Koike: Preliminary performance analysis of flex power FPGA, a power reconfigurable device with fine granularity. FPGA 2004: 257
1998
16	EE	Hayato Yamana, Hanpei Koike, Yuetsu Kodama, Hirofumi Sakane, Yoshinori Yamaguchi: Fast Speculative Search Engine on the Highly Parallel Computer EM-X. SIGIR 1998: 390
1997
15	EE	Yuetsu Kodama, Hirofumi Sakane, Hanpei Koike, Mitsuhisa Sato, Shuichi Sakai, Yoshinori Yamaguchi: Parallel Execution of Radix Sort Program Using Fine-Grain Communication. IEEE PACT 1997: 136-145
1994
14		Hidemoto Nakada, Takuya Araki, Hanpei Koike, Hidehiko Tanaka: A Fleng Compiler for PIE64. IFIP PACT 1994: 257-266
13		Jun'ichi Tatemura, Hanpei Koike, Hidehiko Tanaka: A Performance Debugger for a Parallel Logic Programming Language Fleng. Theory and Practice of Parallel Programming 1994: 284-299
1993
12		Kentaro Shimada, Hanpei Koike, Hidehiko Tanaka: The Instruction Set Architecture of the Inference Processor UNIRED II. Architectures and Compilation Techniques for Fine and Medium Grain Parallelism 1993: 117-128
11		Yasuo Hidaka, Hanpei Koike, Hidehiko Tanaka: Multiple Threads in Cyclic Register Windows. ISCA 1993: 131-142
10		Jun'ichi Tatemura, Hanpei Koike, Hidehiko Tanaka: Control and Data Flow Visualization for Parallel Logic Programs on a Multi-window Debugger HyperDEBU. PARLE 1993: 414-425
9		Kentaro Shimada, Hanpei Koike, Hidehiko Tanaka: UNIRED II: The High Performance Inference Processor for the Parallel Inference Machine PIE64. New Generation Comput. 11(3): 251-269 (1993)
1992
8		Kentaro Shimada, Hanpei Koike, Hidehiko Tanaka: UNIRED II: The High Performance Inference Processor for the Parallel Inference Machine PIE64. FGCS 1992: 715-722
7		Yasuo Hidaka, Hanpei Koike, Hidehiko Tanaka: Architecture of Parallel Management Kernel for PIE64. PARLE 1992: 685-700
6		Jun'ichi Tatemura, Hanpei Koike, Hidehiko Tanaka: HyperDEBU: A Multiwindow Debugger for Parallel Logic Programs. Programming Environments for Parallel Computing 1992: 87-105
1991
5		Yasuo Hidaka, Hanpei Koike, Jun'ichi Tatemura, Hidehiko Tanaka: A Static Load Partitioning Method based on Execution Profile for Committed Choice Languages. ISLP 1991: 470-484
1989
4		Lu Xu, Hanpei Koike, Hidehiko Tanaka: Distributed Garbage Collection for the Parallel Inference Machine PIE64. IFIP Congress 1989: 1161-1166
3		Lu Xu, Hanpei Koike, Hidehiko Tanaka: Distributed Garbage Collection for the Parallel Inference Engine PIE64. NACLP 1989: 922-941
1988
2		Hanpei Koike, Hidehiko Tanaka: Multi-Context Processing and Data Balancing Mechanism of the Parallel Inference Machine PIE64. FGCS 1988: 970-977
1986
1		Hanpei Koike, Hidehiko Tanaka: Fast Execution Mechanisms of Parallel Inference Engine PIE: PIEpelined Goal Rewriting and Goal Multicasting. LP 1986: 159-169

Coauthor Index

1	Takuya Araki	[14]
2	Kazuhiko Endo	[23]
3	Yasuo Hidaka	[5] [7] [11]
4	Masakazu Hioki	[17] [19] [20] [21] [22]
5	Takashi Kawanami	[17] [19] [20] [21] [22]
6	Yuetsu Kodama	[15] [16]
7	Yongxun Liu	[23]
8	Meishoku Masahara	[23]
9	Akira Masaki	[18]
10	Takashi Matsukawa	[23]
11	Yohei Matsumoto	[18] [20] [21] [22]
12	Hiroshi Nagase	[17]
13	Hidemoto Nakada	[14]
14	Tadashi Nakagawa	[17] [19] [20] [21] [22]
15	Shin-ichi O'Uchi	[23]
16	Shuichi Sakai	[15]
17	Kunihiro Sakamoto	[23]
18	Hirofumi Sakane	[15] [16]
19	Mitsuhisa Sato	[15]
20	Toshihiro Sekigawa	[17] [19] [20] [21] [22] [23]
21	Kentaro Shimada	[8] [9] [12]
22	Eiichi Suzuki	[23]
23	Hidehiko Tanaka	[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14]
24	Jun'ichi Tatemura	[5] [6] [10] [13]
25	Toshiyuki Tsutsumi	[17] [19] [20] [21] [22]
26	Lu Xu	[3] [4]
27	Yoshinori Yamaguchi	[15] [16]
28	Hayato Yamana	[16]

Colors in the list of coauthors