| |
| 1994 | ||
|---|---|---|
| 1 | EE | V. Szwarc, L. Desormeaux, W. Wong, C. P. S. Yeung, C. H. Chan, Tad A. Kwasniewski: A chip set for pipeline and parallel pipeline FFT architectures. VLSI Signal Processing 8(3): 253-265 (1994) |
| 1 | C. H. Chan | [1] |
| 2 | L. Desormeaux | [1] |
| 3 | Tad A. Kwasniewski | [1] |
| 4 | V. Szwarc | [1] |
| 5 | W. Wong | [1] |