2007 |
14 | EE | Shin'ichi Kouyama,
Tomonori Izumi,
Hiroyuki Ochi,
Yukihiro Nakamura:
A Simulation Platform for Designing Cell-Array-Based Self-Reconfigurable Architecture.
IEICE Transactions 90-A(4): 784-791 (2007) |
13 | EE | Takahiro Murooka,
Akira Nagoya,
Toshiaki Miyazaki,
Hiroyuki Ochi,
Yukihiro Nakamura:
Network Processor for High-Speed Network and Quick Programming.
Journal of Circuits, Systems, and Computers 16(1): 65-79 (2007) |
2006 |
12 | EE | Kentaro Nakahara,
Shin'ichi Kouyama,
Tomonori Izumi,
Hiroyuki Ochi,
Yukihiro Nakamura:
Autonomous-repair cell for fault tolerant dynamic-reconfigurable devices.
FPGA 2006: 224 |
11 | EE | Kentaro Nakahara,
Shin'ichi Kouyama,
Tomonori Izumi,
Hiroyuki Ochi,
Yukihiro Nakamura:
Fault Tolerant Reconfigurable Device Based on Autonomous-Repair Cells.
FPL 2006: 1-6 |
10 | EE | Hiroki Sugano,
Hiroshi Tsutsui,
Takahiko Masuzaki,
Takao Onoye,
Hiroyuki Ochi,
Yukihiro Nakamura:
Efficient memory architecture for JPEG2000 entropy codec.
ISCAS 2006 |
9 | EE | Ryusuke Miyamoto,
Hiroki Sugano,
Hiroaki Saito,
Hiroshi Tsutsui,
Hiroyuki Ochi,
Ken'ichi Hatanaka,
Yukihiro Nakamura:
Pedestrian Recognition in Far-Infrared Images by Combining Boosting-Based Detection and Skeleton-Based Stochastic Tracking.
PSIVT 2006: 483-494 |
8 | EE | Kentaro Nakahara,
Shin'ichi Kouyama,
Tomonori Izumi,
Hiroyuki Ochi,
Yukihiro Nakamura:
Fault Tolerant Dynamic Reconfigurable Device Based on EDAC with Rollback.
IEICE Transactions 89-A(12): 3652-3658 (2006) |
7 | EE | Hiroyuki Ochi,
Shigeaki Tagashira,
Satoshi Fujita:
A Localization Scheme for Sensor Networks Based on Wireless Communication with Anchor Groups.
IEICE Transactions 89-D(5): 1614-1621 (2006) |
2005 |
6 | EE | Hiroyuki Ochi,
Shigeaki Tagashira,
Satoshi Fujita:
A Localization Scheme for Sensor Networks based onWireless Communication with Anchor Groups.
ICPADS (1) 2005: 299-305 |
5 | EE | Tomonori Izumi,
Shin'ichi Kouyama,
Hiroyuki Ochi,
Yukihiro Nakamura:
An Integrated Approach of Variable Ordering and Logic Mapping into LUT-Array-Based PLD.
IEICE Transactions 88-A(4): 907-914 (2005) |
2000 |
4 | EE | Hirofumi Sakamoto,
Ken'ichiro Uda,
Bu-Y. Lee,
Hiroyuki Ochi,
Kazuo Taki,
Takao Tsuda:
A 16-bit redundant binary multiplier using low-power pass-transistor logic SPL.
ASP-DAC 2000: 33-34 |
1993 |
3 | EE | Hiroyuki Ochi,
Koichi Yasuoka,
Shuzo Yajima:
Breadth-first manipulation of very large binary-decision diagrams.
ICCAD 1993: 48-55 |
1991 |
2 | | Hiromi Hiraishi,
Kiyoharu Hamaguchi,
Hiroyuki Ochi,
Shuzo Yajima:
Vectorized Symbolic Model Checking of Computation Tree Logic for Sequential Machine Verification.
CAV 1991: 214-224 |
1 | EE | Hiroyuki Ochi,
Nagisa Ishiura,
Shuzo Yajima:
Breadth-First Manipulation of SBDD of Boolean Functions for Vector Processing.
DAC 1991: 413-416 |