B. Suresh

2005
3	EE	B. Suresh, V. Visvanathan, R. S. Krishnan, H. S. Jamadagni: Application of Alpha Power Law Models to PLL Design Methodology. VLSI Design 2005: 768-773
2003
2	EE	B. Suresh, R. Nadarajan: Object Oriented Parallel Programming Model on a Network of Workstations. International Conference on Computational Science 2003: 1000-1010
2000
1	EE	B. Suresh, Biswadeep Chaterjee, R. Harinath: Synthesizable RAM-Alternative to Low Configuration Compiler Memory for Die Area Reduction. VLSI Design 2000: 512-517

Coauthor Index

1	Biswadeep Chaterjee	[1]
2	R. Harinath	[1]
3	H. S. Jamadagni	[3]
4	R. S. Krishnan	[3]
5	R. Nadarajan	[2]
6	V. Visvanathan	[3]

Colors in the list of coauthors