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B. Suresh

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2005
3EEB. Suresh, V. Visvanathan, R. S. Krishnan, H. S. Jamadagni: Application of Alpha Power Law Models to PLL Design Methodology. VLSI Design 2005: 768-773
2003
2EEB. Suresh, R. Nadarajan: Object Oriented Parallel Programming Model on a Network of Workstations. International Conference on Computational Science 2003: 1000-1010
2000
1EEB. Suresh, Biswadeep Chaterjee, R. Harinath: Synthesizable RAM-Alternative to Low Configuration Compiler Memory for Die Area Reduction. VLSI Design 2000: 512-517

Coauthor Index

1Biswadeep Chaterjee [1]
2R. Harinath [1]
3H. S. Jamadagni [3]
4R. S. Krishnan [3]
5R. Nadarajan [2]
6V. Visvanathan [3]

Colors in the list of coauthors

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)