dblp.uni-trier.dewww.uni-trier.de

J. V. R. Ravindra

List of publications from the DBLP Bibliography Server - FAQ
Coauthor Index - Ask others: ACM DL/Guide - CiteSeer - CSB - Google - MSN - Yahoo

2008
6EEJ. V. R. Ravindra, M. B. Srinivas: Generic sub-space algorithm for generating reduced order models of linear time varying vlsi circuits. ACM Great Lakes Symposium on VLSI 2008: 111-114
2007
5EEJ. V. R. Ravindra, M. B. Srinivas: A Statistical Model for Estimating the Effect of Process Variations on Delay and Slew Metrics for VLSI Interconnects. DSD 2007: 325-330
4EEJ. V. R. Ravindra, M. B. Srinivas: Delay and Energy Efficient Coding Techniques for Capacitive Interconnects. Journal of Circuits, Systems, and Computers 16(6): 929-942 (2007)
2006
3EEK. S. Sainarayanan, J. V. R. Ravindra, M. B. Srinivas: Minimizing Simultaneous Switching Noise (SSN) using Modified Odd/Even Bus Invert Method. DELTA 2006: 336-339
2EEK. S. Sainarayanan, J. V. R. Ravindra, M. B. Srinivas: A novel, coupling driven, low power bus coding technique for minimizing capacitive crosstalk in VLSI interconnects. ISCAS 2006
2005
1 K. S. Sainarayanan, J. V. R. Ravindra, M. B. Srinivas: A novel deep submicron low power bus coding technique. Circuits, Signals, and Systems 2005: 154-159

Coauthor Index

1K. S. Sainarayanan [1] [2] [3]
2M. B. Srinivas [1] [2] [3] [4] [5] [6]

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)