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Atsufumi Shibayama

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1997
2EETomohiro Yoneda, Atsufumi Shibayama, Takashi Nanya: Verification of asynchronous logic circuit design using process algebra. Systems and Computers in Japan 28(8-9): 33-43 (1997)
1993
1 Tomohiro Yoneda, Atsufumi Shibayama, Bernd-Holger Schlingloff, Edmund M. Clarke: Efficient Verification of Parallel Real-Time Systems. CAV 1993: 321-346

Coauthor Index

1Edmund M. Clarke [1]
2Takashi Nanya [2]
3Bernd-Holger Schlingloff [1]
4Tomohiro Yoneda [1] [2]

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)