1997 | ||
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2 | EE | Tomohiro Yoneda, Atsufumi Shibayama, Takashi Nanya: Verification of asynchronous logic circuit design using process algebra. Systems and Computers in Japan 28(8-9): 33-43 (1997) |
1993 | ||
1 | Tomohiro Yoneda, Atsufumi Shibayama, Bernd-Holger Schlingloff, Edmund M. Clarke: Efficient Verification of Parallel Real-Time Systems. CAV 1993: 321-346 |
1 | Edmund M. Clarke | [1] |
2 | Takashi Nanya | [2] |
3 | Bernd-Holger Schlingloff | [1] |
4 | Tomohiro Yoneda | [1] [2] |