| 2001 |
|---|
| 8 | EE | Shanq-Jang Ruan,
Rung-Ji Shang,
Feipei Lai,
Kun-Lin Tsai:
A bipartition-codec architecture to reduce power in pipelinedcircuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 20(2): 343-348 (2001) |
| 7 | EE | Shura Hayryan,
Chin-Kun Hu,
Shun-Yun Hu,
Rung-Ji Shang:
Multicanonical parallel simulations of proteins with continuous potentials.
Journal of Computational Chemistry 22(12): 1287-1296 (2001) |
| 2000 |
|---|
| 6 | EE | Edwin Naroska,
Rung-Ji Shang,
Feipei Lai,
Uwe Schwiegelshohn:
Hybrid Parallel Circuit Simulation Approaches.
IEEE PACT 2000: 261-270 |
| 5 | EE | Kuang-Hung Pan,
Hsiao-Kuang Wu,
Rung-Ji Shang,
Feipei Lai:
Performance analysis of broadcast in mobile ad hoc networks with synchronized and non-synchronized reception.
Computer Communications 23(5-6): 511-524 (2000) |
| 1999 |
|---|
| 4 | | Kuang-Hung Pan,
Hsiao-Kuang Wu,
Rung-Ji Shang,
Feipei Lai:
Performance Analysis of Broadcast in Synchronized Multihop Wireless Networks.
HPCN Europe 1999: 493-502 |
| 3 | EE | Shanq-Jang Ruan,
Rung-Ji Shang,
Feipei Lai,
Shyh-Jong Chen,
Xian-Jun Huang:
A bipartition-codec architecture to reduce power in pipelined circuits.
ICCAD 1999: 84-90 |
| 1995 |
|---|
| 2 | EE | Tzer-Shyong Chen,
Feipei Lai,
Rung-Ji Shang:
A Simple Tree Pattern Matching Algorithm for Code Generator.
COMPSAC 1995: 162-169 |
| 1992 |
|---|
| 1 | EE | Meng-chou Chang,
Feipei Lai,
Rung-Ji Shang:
Exploiting instruction-level parallelism with the conjugate register file scheme.
MICRO 1992: 29-32 |
