| |
| 1999 | ||
|---|---|---|
| 1 | EE | Shanq-Jang Ruan, Rung-Ji Shang, Feipei Lai, Shyh-Jong Chen, Xian-Jun Huang: A bipartition-codec architecture to reduce power in pipelined circuits. ICCAD 1999: 84-90 |
| 1 | Xian-Jun Huang | [1] |
| 2 | Feipei Lai | [1] |
| 3 | Shanq-Jang Ruan | [1] |
| 4 | Rung-Ji Shang | [1] |