| 2006 |
|---|
| 7 | EE | Kun-Lin Tsai,
Ju-Yueh Lee,
Shanq-Jang Ruan,
Feipei Lai:
Low power scheduling method using multiple supply voltages.
ISCAS 2006 |
| 2005 |
|---|
| 6 | EE | Kun-Lin Tsai,
Szu-Wei Chaung,
Feipei Lai,
Shanq-Jang Ruan:
A low power scheduling method using dual V/sub dd/ and dual V/sub th/.
ISCAS (1) 2005: 684-687 |
| 5 | EE | Shanq-Jang Ruan,
Kun-Lin Tsai,
Edwin Naroska,
Feipei Lai:
Bipartitioning and encoding in low-power pipelined circuits.
ACM Trans. Design Autom. Electr. Syst. 10(1): 24-32 (2005) |
| 2003 |
|---|
| 4 | EE | Kun-Lin Tsai,
Feipei Lai,
Shanq-Jang Ruan,
Szu-Wei Chaung:
State Reordering for Low Power Combinational Logic.
Asia-Pacific Computer Systems Architecture Conference 2003: 268-276 |
| 2001 |
|---|
| 3 | EE | Po-Hung Chen,
Shanq-Jang Ruan,
Kuen-Pin Wu,
Dai-Xun Hu,
Feipei Lai,
Kun-Lin Tsai:
An entropy-based algorithm to reduce area overhead for bipartition-codec architecture.
ISCAS (5) 2001: 49-52 |
| 2 | EE | Shanq-Jang Ruan,
Jen-Chiun Lin,
Po-Hung Chen,
Kun-Lin Tsai,
Feipei Lai:
Synthesis of partition-codec architecture for low power and small area circuit design.
ISCAS (5) 2001: 523-526 |
| 1 | EE | Shanq-Jang Ruan,
Rung-Ji Shang,
Feipei Lai,
Kun-Lin Tsai:
A bipartition-codec architecture to reduce power in pipelinedcircuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 20(2): 343-348 (2001) |
