| 2008 |
|---|
| 8 | EE | Sanjay V. Rajopadhye,
Gautam Gupta,
Lakshminarayanan Renganarayanan:
A domain specific interconnect for reconfigurable computing.
LCTES 2008: 79-88 |
| 7 | EE | Lakshminarayanan Renganarayanan,
Sanjay V. Rajopadhye:
Positivity, posynomials and tile size selection.
SC 2008: 55 |
| 2007 |
|---|
| 6 | EE | Lakshminarayanan Renganarayanan,
Manjukumar Harthikote-Matha,
Rinku Dewri,
Sanjay V. Rajopadhye:
Towards Optimal Multi-level Tiling for Stencil Computations.
IPDPS 2007: 1-10 |
| 5 | EE | Lakshminarayanan Renganarayanan,
DaeGon Kim,
Sanjay V. Rajopadhye,
Michelle Mills Strout:
Parameterized tiled loops for free.
PLDI 2007: 405-414 |
| 4 | EE | DaeGon Kim,
Lakshminarayanan Renganarayanan,
Dave Rostron,
Sanjay V. Rajopadhye,
Michelle Mills Strout:
Multi-level tiling: M for the price of one.
SC 2007: 51 |
| 2005 |
|---|
| 3 | EE | Lakshminarayanan Renganarayanan,
U. Ramakrishna,
Sanjay V. Rajopadhye:
Combined ILP and Register Tiling: Analytical Model and Optimization Framework.
LCPC 2005: 244-258 |
| 2004 |
|---|
| 2 | EE | Lakshminarayanan Renganarayanan,
Sanjay V. Rajopadhye:
A Geometric Programming Framework for Optimal Multi-Level Tiling.
SC 2004: 18 |
| 2003 |
|---|
| 1 | EE | Lakshminarayanan Renganarayanan,
Sanjay V. Rajopadhye:
Switched Memory Architectures-Moving Beyond Systolic Arrays.
ASAP 2003: 28-39 |
