| |
| 2008 | ||
|---|---|---|
| 3 | EE | Pao-Lung Chen: Jitter simulation and measurement of an all-digital clock generator with dynamic frequency counting loop. ISCAS 2008: 2554-2557 |
| 2005 | ||
| 2 | EE | Pao-Lung Chen, Ching-Che Chung, Chen-Yi Lee: An all-digital PLL with cascaded dynamic phase average loop for wide multiplication range applications. ISCAS (5) 2005: 4875-4878 |
| 1 | EE | Pao-Lung Chen, Chen-Yi Lee: A Standard Cell-Based Frequency Synthesizer with Dynamic Frequency Counting. IEICE Transactions 88-A(12): 3554-3563 (2005) |
| 1 | Ching-Che Chung | [2] |
| 2 | Chen-Yi Lee | [1] [2] |