Jer-Min Tsai
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1995
1
EE
Chen-Yi Lee
, Jer-Min Tsai: A shift register architecture for high-speed data sorting.
VLSI Signal Processing 11
(3): 273-280 (1995)
Coauthor
Index
1
Chen-Yi Lee
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1
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Copyright ©
Sun May 17 03:24:02 2009 by
Michael Ley
(
ley@uni-trier.de
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