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| 2006 | ||
|---|---|---|
| 3 | EE | Duo Sheng, Ching-Che Chung, Chen-Yi Lee: A Fast-Lock-In ADPLL with High-Resolution and Low-Power DCO for SoC Applications. APCCAS 2006: 105-108 |
| 2 | EE | Tsu-Ming Liu, Ching-Che Chung, Chen-Yi Lee, Ting-An Lin, Sheng-Zen Wang: Design of a 125muW, fully-scalable MPEG-2 and H.264/AVC video decoder for mobile applications. DAC 2006: 288-289 |
| 2005 | ||
| 1 | EE | Pao-Lung Chen, Ching-Che Chung, Chen-Yi Lee: An all-digital PLL with cascaded dynamic phase average loop for wide multiplication range applications. ISCAS (5) 2005: 4875-4878 |
| 1 | Pao-Lung Chen | [1] |
| 2 | Chen-Yi Lee | [1] [2] [3] |
| 3 | Ting-An Lin | [2] |
| 4 | Tsu-Ming Liu | [2] |
| 5 | Duo Sheng | [3] |
| 6 | Sheng-Zen Wang | [2] |