| |
| 2007 | ||
|---|---|---|
| 3 | EE | Jin-Tai Yan, Bo-Yi Chiang: Timing-Constrained Yield-Driven Wiring Reconstruction for Critical Area Minimization. VLSI Design 2007: 899-906 |
| 2006 | ||
| 2 | EE | Jin-Tai Yan, Bo-Yi Chiang, Shi-Qin Huang: Width and Timing-Constrained Wire Sizing for Critical Area Minimization. APCCAS 2006: 1276-1279 |
| 1 | EE | Jin-Tai Yan, Bo-Yi Chiang, Chia-Fang Lee: Timing-constrained yield-driven wire sizing for critical area minimization. ISCAS 2006 |
| 1 | Shi-Qin Huang | [2] |
| 2 | Chia-Fang Lee | [1] |
| 3 | Jin-Tai Yan | [1] [2] [3] |