Ming-Ching Huang
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2006
1
EE
Jin-Tai Yan
,
Yen-Hsiang Chen
,
Chia-Fang Lee
, Ming-Ching Huang: Multilevel timing-constrained full-chip routing in hierarchical quad-grid model.
ISCAS 2006
Coauthor
Index
1
Yen-Hsiang Chen
[
1
]
2
Chia-Fang Lee
[
1
]
3
Jin-Tai Yan
[
1
]
Copyright ©
Sun May 17 03:24:02 2009 by
Michael Ley
(
ley@uni-trier.de
)
