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| 1985 | ||
|---|---|---|
| 1 | EE | Chung-Yu Wu, Jen-Sheng Hwang, Chih Chang, Ching-Chu Chang: An Efficient Timing Model for CMOS Combinational Logic Gates. IEEE Trans. on CAD of Integrated Circuits and Systems 4(4): 636-650 (1985) |
| 1 | Ching-Chu Chang | [1] |
| 2 | Jen-Sheng Hwang | [1] |
| 3 | Chung-Yu Wu | [1] |