| |
| 1994 | ||
|---|---|---|
| 2 | Shu-Yuan Chin, Chung-Yu Wu: An Alorithmic Analog-to-Digital Converter with low Ratio-and Gain-Sensitivities and 4N-Clock Conversion Cycle. ISCAS 1994: 325-328 | |
| 1993 | ||
| 1 | Shu-Yuan Chin, Chung-Yu Wu: A Ratio-independent and Gain-insensitive Algorithmic Analog-to-digital Converter. ISCAS 1993: 1200-1203 | |
| 1 | Chung-Yu Wu | [1] [2] |