Yu-Lung Hsu
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2002
1
EE
Yu-Lung Hsu,
Sying-Jyan Wang
: Retiming-based logic synthesis for low-power.
ISLPED 2002
: 275-278
Coauthor
Index
1
Sying-Jyan Wang
[
1
]
Copyright ©
Sun May 17 03:24:02 2009 by
Michael Ley
(
ley@uni-trier.de
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