SIGARCH Computer Architecture News, Volume 31

Volume 31, Number 1, March 2003

• Jack B. Dennis:
  Fresh Breeze: a multiprocessor chip architecture guided by modular programming principles. 7-15
  Electronic Edition (ACM DL) BibTeX
• David Morano, Alireza Khalafi, David R. Kaeli, Augustus K. Uht:
  Realizing high IPC through a scalable memory-latency tolerant multipath microarchitecture. 16-25
  Electronic Edition (ACM DL) BibTeX
• George Almási, Calin Cascaval, José G. Castaños, Monty Denneau, Derek Lieber, José E. Moreira, Henry S. Warren Jr.:
  Dissecting Cyclops: a detailed analysis of a multithreaded architecture. 26-38
  Electronic Edition (ACM DL) BibTeX
• Mohamed M. Zahran:
  On cache memory hierarchy for Chip-Multiprocessor. 39-48
  Electronic Edition (ACM DL) BibTeX
• Gary Gréwal, Tom Wilson, Andrew Morton:
  An EGA approach to the compile-time assignment of data to multiple memories in digital-signal processors. 49-59
  Electronic Edition (ACM DL) BibTeX
• Ulrich Ramacher, Nico Brüls, J. A. Ulrich Hachmann, Jens Harnisch, Wolfgang Raab, Axel Techmer:
  100 GOPS vision processor for automotive applications. 60-68
  Electronic Edition (ACM DL) BibTeX
• Nikos Pitsianis, Gerald G. Pechanek:
  Indirect VLIW memory allocation for the ManArray multiprocessor DSP. 69-74
  Electronic Edition (ACM DL) BibTeX
• Naohiko Shimizu, Ken Takatori:
  A transparent Linux super page kernel for Alpha, Sparc64 and IA32: reducing TLB misses of applications. 75-84
  Electronic Edition (ACM DL) BibTeX
• Alessio Bechini, Pierfrancesco Foglia, Cosimo Antonio Prete:
  Fine-grain design space exploration for a cartographic SoC multiprocessor. 85-92
  Electronic Edition (ACM DL) BibTeX

• Mark Thorson:
  Internet nuggets. 93-96
  Electronic Edition (ACM DL) BibTeX

Volume 31, Number 2, May 2003

Volume 31, Number 3, June 2003

• Anthony S. Fong:
  A computer architecture with access control and cache option tags on individual instruction operands. 1-5
  Electronic Edition (ACM DL) BibTeX
• Edwin J. Tan, Wendi Beth Heinzelman:
  DSP architectures: past, present and futures. 6-19
  Electronic Edition (ACM DL) BibTeX
• Lucian N. Vintan, Marius Sbera, Ioan Z. Mihu, Adrian Florea:
  An alternative to branch prediction: pre-computed branches. 20-29
  Electronic Edition (ACM DL) BibTeX
• Mark Heinrich, Mainak Chaudhuri:
  Ocean warning: avoid drowning. 30-32
  Electronic Edition (ACM DL) BibTeX
• Jean-Louis Lafitte:
  Qualitatively matching computer architecture with Turing machine. 33-41
  Electronic Edition (ACM DL) BibTeX
• Takenori Koushiro, Toshinori Sato, Itsujiro Arita:
  A trace-level value predictor for Contrail processors. 42-47
  Electronic Edition (ACM DL) BibTeX

• Mark Thorson:
  Internet nuggets. 48-54
  Electronic Edition (ACM DL) BibTeX

Volume 31, Number 4, September 2003

• Mikkel Thorup:
  Combinatorial power in multimedia processors. 5-11
  Electronic Edition (ACM DL) BibTeX
• Gary K. W. Hau, Anthony S. Fong, Mok Pak Lun:
  Support of Java API for the jHISC system. 12-17
  Electronic Edition (ACM DL) BibTeX
• Mok Pak Lun, Richard Li, Anthony S. Fong:
  Method manipulation in an object-oriented processor. 18-25
  Electronic Edition (ACM DL) BibTeX

• Mark Thorson:
  Internet nuggets. 26-32
  Electronic Edition (ACM DL) BibTeX

Volume 31, Number 5, December 2003

• Kristopher C. Breen, Duncan G. Elliott:
  Aliasing and anti-aliasing in branch history table prediction. 1-4
  Electronic Edition (ACM DL) BibTeX
• Ryan W. S. Yu, Gary K. W. Hau, Anthony S. Fong:
  Test bench for software development of object-oriented processor. 5-9
  Electronic Edition (ACM DL) BibTeX
• Mok Pak Lun, Anthony S. Fong, Gary K. W. Hau:
  Object-oriented processor requirements with instruction analysis of Java programs. 10-15
  Electronic Edition (ACM DL) BibTeX

• Mark Thorson:
  Internet nuggets. 16-21
  Electronic Edition (ACM DL) BibTeX