2008 |
12 | EE | Narayanan Ramanan,
Sonia Khatchadourian,
Jean-Christophe Prévotet,
Lounis Kessal:
Neural network hardware architecture for pattern recognition in the HESS2 project.
ESANN 2008: 343-348 |
2007 |
11 | EE | Si Mahmoud Karabernou,
Lounis Kessal,
Fayçal Terranti:
Erratum to "Real-time FPGA implementation of Hough Transform using gradient and CORDIC algorithm" [Image and Vision Computing 23 (2005) 1009-1017].
Image Vision Comput. 25(6): 1032 (2007) |
2006 |
10 | | Nicolas Abel,
Lounis Kessal,
Sébastien Pillement,
Didier Demigny:
Clear Stream towards Dynamically Reconfigurable Systems on Chip.
ReCoSoC 2006: 98-104 |
2004 |
9 | | Nicolas Abel,
Lounis Kessal,
Didier Demigny:
Design flexibility using fpga dynamical reconfiguration.
ICIP 2004: 2821-2824 |
2003 |
8 | EE | Lounis Kessal,
Nicolas Abel,
Didier Demigny:
Real-time image processing with dynamically reconfigurable architecture.
Real-Time Imaging 9(5): 297-313 (2003) |
2001 |
7 | | P. Lamaty,
B. Mazar,
Didier Demigny,
Lounis Kessal,
M. Karabernou:
Two ASIC for Low and Middle Levels of Real Time Image Processing.
VLSI-SOC 2001: 3-14 |
6 | | Didier Demigny,
Lounis Kessal,
J. Pons:
Fast Recursive Implementation of the Gaussian Filter.
VLSI-SOC 2001: 39-49 |
5 | | Lounis Kessal,
R. Bourguiba,
Didier Demigny,
N. Boudouani,
M. Karabernou:
Reconfigurable Architecture Using High Speed FPGA.
VLSI-SOC 2001: 75-86 |
2000 |
4 | EE | Didier Demigny,
Lounis Kessal,
R. Bourguiba,
N. Boudouani:
How to Use High Speed Reconfigurable FPGA for Real Time Image Processing?
CAMP 2000: 240- |
3 | | Lounis Kessal,
Didier Demigny,
N. Boudouani,
R. Bourgiba:
Reconfigurable Hardware for Real Time Image Processing.
ICIP 2000 |
1997 |
2 | EE | F. G. Lorca,
Lounis Kessal,
Didier Demigny:
Efficient ASIC and FPGA Implementations of IIR Filters for Real Time Edge Detection.
ICIP (2) 1997: 406-409 |
1995 |
1 | EE | Didier Demigny,
F. G. Lorca,
Lounis Kessal:
Evaluation of edge detectors performances with a discrete expression of Canny's criteria.
ICIP 1995: 2169-2172 |