| 2006 |
|---|
| 10 | EE | Erik Reeber,
Jun Sawada:
Combining ACL2 and an automated verification tool to verify a multiplier.
ACL2 2006: 63-70 |
| 9 | EE | Jun Sawada,
Erik Reeber:
ACL2SIX: A Hint used to Integrate a Theorem Prover and an Automated Verification Tool.
FMCAD 2006: 161-170 |
| 8 | EE | Wendy Belluomini,
Damir Jamsek,
Andrew K. Martin,
Chandler McDowell,
Robert K. Montoye,
Hung C. Ngo,
Jun Sawada:
Limited switch dynamic logic circuits for high-speed low-power circuit design.
IBM Journal of Research and Development 50(2-3): 277-286 (2006) |
| 2002 |
|---|
| 7 | EE | Jun Sawada,
Ruben Gamboa:
Mechanical Verification of a Square Root Algorithm Using Taylor's Theorem.
FMCAD 2002: 274-291 |
| 6 | | Jun Sawada,
Warren A. Hunt Jr.:
Verification of FM9801: An Out-of-Order Microprocessor Model with Speculative Execution, Exceptions, and Program-Modifying Capability.
Formal Methods in System Design 20(2): 187-222 (2002) |
| 2001 |
|---|
| 5 | EE | H. Peter Hofstee,
Jun Sawada:
Derivation of a rotator circuit with homogeneous interconnect.
Inf. Process. Lett. 77(2-4): 131-135 (2001) |
| 2000 |
|---|
| 4 | EE | Jun Sawada,
Warren A. Hunt Jr.:
Hardware Modeling Using Function Encapsulation.
FMCAD 2000: 234-245 |
| 1999 |
|---|
| 3 | EE | Jun Sawada,
Warren A. Hunt Jr.:
Results of the Verification of a Complex Pipelined Machine Model.
CHARME 1999: 313-316 |
| 1998 |
|---|
| 2 | | Jun Sawada,
Warren A. Hunt Jr.:
Processor Verification with Precise Exeptions and Speculative Execution.
CAV 1998: 135-146 |
| 1997 |
|---|
| 1 | | Jun Sawada,
Warren A. Hunt Jr.:
Trace Table Based Approach for Pipeline Microprocessor Verification.
CAV 1997: 364-375 |
