2007 |
15 | EE | Konosuke Watanabe,
Tomohiro Otsuka,
Junichiro Tsuchiya,
Hiroaki Nishi,
Junji Yamamoto,
Noboru Tanabe,
Tomohiro Kudoh,
Hideharu Amano:
Martini: A Network Interface Controller Chip for High Performance Computing with Distributed PCs.
IEEE Trans. Parallel Distrib. Syst. 18(9): 1282-1295 (2007) |
2006 |
14 | EE | Hidehiro Toyoda,
Shinji Nishimura,
Michitaka Okuno,
Kouji Fukuda,
Kouji Nakahara,
Hiroaki Nishi:
100-Gb/s Physical-Layer Architecture for Next-Generation Ethernet.
IEICE Transactions 89-B(3): 696-703 (2006) |
13 | EE | Michitaka Okuno,
Shinji Nishimura,
Shin-ichi Ishida,
Hiroaki Nishi:
Cache-Based Network Processor Architecture: Evaluation with Real Network Traffic.
IEICE Transactions 89-C(11): 1620-1628 (2006) |
2005 |
12 | | Yoshihiro Hamada,
Hiroaki Nishi,
Akira Kitamura,
Noboru Tanabe,
Hideharu Amano,
Hironori Nakajo:
A Packet Forwarding Layer for DIMMnet and its Hardware Implementation.
PDPTA 2005: 461-467 |
11 | EE | Michitaka Okuno,
Shin-ichi Ishida,
Hiroaki Nishi:
Low-Power Network-Packet-Processing Architecture Using Process-Learning Cache for High-End Backbone Router.
IEICE Transactions 88-C(4): 536-543 (2005) |
2004 |
10 | EE | Michiaki Muraoka,
Hiroaki Nishi,
Rafael K. Morizawa,
Hideaki Yokota,
Hideyuki Hamada:
Design methodology for SoC arthitectures based on reusable virtual cores.
ASP-DAC 2004: 256-262 |
2003 |
9 | | Tomohiro Otsuka,
Konosuke Watanabe,
Junichiro Tsuchiya,
Hiroshi Harada,
Junji Yamamoto,
Hiroaki Nishi,
Tomohiro Kudoh,
Hideharu Amano:
Performance Evaluation of a Prototype of RHiNET-2: A Network-based Distributed Parallel Computing System.
Applied Informatics 2003: 738-743 |
8 | EE | Konosuke Watanabe,
Tomohiro Otsuka,
Junichiro Tsuchiya,
Hideharu Amano,
Hiroshi Harada,
Junji Yamamoto,
Hiroaki Nishi,
Tomohiro Kudoh:
Performance Evaluation of RHiNET-2/NI: A Network Interface for Distributed Parallel Computing Systems.
CCGRID 2003: 318-325 |
2002 |
7 | | Noboru Tanabe,
Junji Yamamoto,
Hiroaki Nishi,
Tomohiro Kudoh,
Yoshihiro Hamada,
Hironori Nakajo,
Hideharu Amano:
Low Latency High Bandwidth Message Transfer Mechanisms for a Network Interface Plugged into a Memory Slot.
Cluster Computing 5(1): 7-17 (2002) |
2001 |
6 | EE | Yulu Yang,
Akira Funahashi,
Akiya Jouraku,
Hiroaki Nishi,
Hideharu Amano,
Toshinori Sueyoshi:
Recursive Diagonal Torus: An Interconnection Network for Massively Parallel Computers.
IEEE Trans. Parallel Distrib. Syst. 12(7): 701-715 (2001) |
5 | EE | Hiroaki Nishi,
Koji Tasho,
Tomohiro Kudoh,
Hideharu Amano:
A network switch for supporting high-performance parallel processing by computers distributed in local areas.
Systems and Computers in Japan 32(14): 24-33 (2001) |
2000 |
4 | EE | Noboru Tanabe,
Junji Yamamoto,
Hiroaki Nishi,
Tomohiro Kudoh,
Yoshihiro Hamada,
Hironori Nakajo,
Hideharu Amano:
MEMOnet : Network interface plugged into a memory slot.
CLUSTER 2000: 17-16 |
3 | EE | Hiroaki Nishi,
Koji Tasho,
Junji Yamamoto,
Tomohiro Kudoh,
Hideharu Amano:
A Local Area System Network RHinet-1: A Network for High Performance Parallel Computing.
HPDC 2000: 296-297 |
2 | EE | Noboru Tanabe,
Junji Yamamoto,
Hiroaki Nishi,
Tomohiro Kudoh,
Yoshihiro Hamada,
Hironori Nakajo,
Hideharu Amano:
On-the-fly Sending: A Low Latency High Bandwidth Message Transfer Mechanism.
ISPAN 2000: 186-194 |
1 | | Shinji Nishimura,
K. Harasawa,
N. Matsudaira,
S. Akutsu,
Tomohiro Kudoh,
Hiroaki Nishi,
Hideharu Amano:
RHiNET-2/SW a Hight-throughput, Compact Network-switch Using 8.8-Gbit/s Optical Interconnection.
New Generation Comput. 18(2): 187- (2000) |