| 2008 |
|---|
| 7 | EE | Jih-Ching Chiu,
Yu-Liang Chou,
Ren-Bang Lin:
The Multi-context Reconfigurable Processing Unit for Fine-grain Computing.
J. Inf. Sci. Eng. 24(3): 965-979 (2008) |
| 2005 |
|---|
| 6 | EE | Jih-Ching Chiu,
Ren-Bang Lin:
FMRPU: Design of Fine-Grain Multi-context Reconfigurable Processing Unit.
Asia-Pacific Computer Systems Architecture Conference 2005: 171-185 |
| 2003 |
|---|
| 5 | EE | Yung-Cheng Ma,
Jih-Ching Chiu,
Tien-Fu Chen,
Chung-Ping Chung:
Variable-size data item placement for load and storage balancing.
Journal of Systems and Software 66(2): 157-166 (2003) |
| 2002 |
|---|
| 4 | EE | Jih-Ching Chiu,
Michael Jin-Yi Wang,
Chung-Ping Chung:
Design of Instruction Address Queue for High Degree X86 Superscalar Architecture.
J. Inf. Sci. Eng. 18(3): 393-409 (2002) |
| 3 | EE | Jih-Ching Chiu,
Michael Jin-Yi Wang,
Chung-Ping Chung:
Design of Instruction Address Queue for High Degree X86 Superscalar Architecture.
J. Inf. Sci. Eng. 18(3): 393-409 (2002) |
| 2000 |
|---|
| 2 | EE | Jih-Ching Chiu,
I-Huan Huang,
Chung-Ping Chung:
Design of Instruction Stream Buffer with Trace Support for X86 Processors.
ICCD 2000: 294-299 |
| 1997 |
|---|
| 1 | EE | Shyh-An Chi,
R.-Ming Shiu,
Jih-Ching Chiu,
Si-En Chang,
Chung-Ping Chung:
Instruction Cache Prefetching with Extended BTB.
ICPADS 1997: 360- |
