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Jiangmin Gu

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2005
6EEYajuan He, Chip-Hong Chang, Jiangmin Gu, Hossam A. H. Fahmy: A novel covalent redundant binary Booth encoder. ISCAS (1) 2005: 69-72
5EEYajuan He, Chip-Hong Chang, Jiangmin Gu: An area efficient 64-bit square root carry-select adder for low power applications. ISCAS (4) 2005: 4082-4085
4EEChip-Hong Chang, Jiangmin Gu, Mingyan Zhang: A review of 0.18-/spl mu/m full adder performances for tree structured arithmetic circuits. IEEE Trans. VLSI Syst. 13(6): 686-695 (2005)
2003
3EEMingyan Zhang, Jiangmin Gu, Chip-Hong Chang: A novel hybrid pass logic with static CMOS output drive full-adder cell. ISCAS (5) 2003: 317-320
2EEJiangmin Gu, Chip-Hong Chang: Ultra low voltage, low power 4-2 compressor for high speed multiplications. ISCAS (5) 2003: 321-324
2002
1EEJiangmin Gu, Chip-Hong Chang, Kiat Seng Yeo: An interconnect optimized floorplanning of a scalar product macrocell. ISCAS (1) 2002: 465-468

Coauthor Index

1Chip-Hong Chang [1] [2] [3] [4] [5] [6]
2Hossam A. H. Fahmy [6]
3Yajuan He [5] [6]
4Kiat Seng Yeo [1]
5Mingyan Zhang [3] [4]

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)