Rakesh Gnana David Jeyasingh

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2008

1 EE Rakesh Gnana David Jeyasingh, Navakanta Bhat: A low power, process invariant keeper for high speed dynamic logic circuits. ISCAS 2008: 1668-1671

2008
1	EE	Rakesh Gnana David Jeyasingh, Navakanta Bhat: A low power, process invariant keeper for high speed dynamic logic circuits. ISCAS 2008: 1668-1671

Coauthor Index

1 Navakanta Bhat [1]