MTDT 1999:
San Jose,
CA,
USA
7th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT '99), August 9-10, 1999, San Jose, CA, USA.
IEEE Computer Society 1999, ISBN 0-7695-0259-8 BibTeX
@proceedings{DBLP:conf/mtdt/1999,
title = {7th IEEE International Workshop on Memory Technology, Design,
and Testing (MTDT '99), August 9-10, 1999, San Jose, CA, USA},
booktitle = {MTDT},
publisher = {IEEE Computer Society},
year = {1999},
isbn = {0-7695-0259-8},
bibsource = {DBLP, http://dblp.uni-trier.de}
}
Tutorial on Low Power SRAMs
Architecture and Applications
Diagnosis and Yield
- Sue Brown, Jeff Campbell, Sherri Griffin, Dick James, Ray Haythornthwaite:
Failure Mechanisms Detected in Memory Chips during Routine Construction Analysis.
34-39
Electronic Edition (link) BibTeX
- Jun Zhao, Fred J. Meyer, Fabrizio Lombardi:
Interconnect Diagnosis of Bus-Connected Multi-RAM Systems.
40-47
Electronic Edition (link) BibTeX
- Julie D. Segal, Sergei Bakarian, Jonathon E. Colburn, Madan Kumar, Chang Hong, Alex Shubat:
Determining Redundancy Requirements for Memory Arrays with Critical Area Analysis.
48-53
Electronic Edition (link) BibTeX
- Doug Malone:
Design Validation of .18 um 1 Ghz Cache and Register Arrays.
54-
Electronic Edition (link) BibTeX
Tutorial on SDRAMs
Memory Testing topics
New Ideas in Technology and Design
Copyright © Sat May 16 23:30:58 2009
by Michael Ley (ley@uni-trier.de)
