| 2007 |
|---|
| 4 | EE | Kentaro Kawakami,
Mitsuhiko Kuroda,
Hiroshi Kawaguchi,
Masahiko Yoshimoto:
Power and Memory Bandwidth Reduction of an H.264/AVC HDTV Decoder LSI with Elastic Pipeline Architecture.
ASP-DAC 2007: 292-297 |
| 2006 |
|---|
| 3 | EE | Yasuhiro Morita,
Hidehiro Fujiwara,
Hiroki Noguchi,
Kentaro Kawakami,
Junichi Miyakoshi,
Shinji Mikami,
Koji Nii,
Hiroshi Kawaguchi,
Masahiko Yoshimoto:
A 0.3-V Operating, Vth-Variation-Tolerant SRAM under DVS Environment for Memory-Rich SoC in 90-nm Technology Era and Beyond.
IEICE Transactions 89-A(12): 3634-3641 (2006) |
| 2 | EE | Kentaro Kawakami,
Jun Takemura,
Mitsuhiko Kuroda,
Hiroshi Kawaguchi,
Masahiko Yoshimoto:
A 50% Power Reduction in H.264/AVC HDTV Video Decoder LSI by Dynamic Voltage Scaling in Elastic Pipeline.
IEICE Transactions 89-A(12): 3642-3651 (2006) |
| 2005 |
|---|
| 1 | EE | Kentaro Kawakami,
Miwako Kanamori,
Yasuhiro Morita,
Jun Takemura,
Masayuki Miyama,
Masahiko Yoshimoto:
Power-Minimum Frequency/Voltage Cooperative Management Method for VLSI Processor in Leakage-Dominant Technology Era.
IEICE Transactions 88-A(12): 3290-3297 (2005) |
