| |
| 2008 | ||
|---|---|---|
| 2 | EE | Igor Keller, King Ho Tam, Vinod Kariat: Challenges in gate level modeling for delay and SI at 65nm and below. DAC 2008: 468-473 |
| 2004 | ||
| 1 | EE | Igor Keller, Ken Tseng, Nishath K. Verghese: A robust cell-level crosstalk delay change analysis. ICCAD 2004: 147-154 |
| 1 | Vinod Kariat | [2] |
| 2 | King Ho Tam | [2] |
| 3 | Ken Tseng | [1] |
| 4 | Nishath K. Verghese | [1] |