| 2008 |
|---|
| 4 | EE | Shuaiqi Wang,
Fule Li,
Yasuaki Inoue:
A 12-bit 3.7-Msample/s Pipelined A/D Converter Based on the Novel Capacitor Mismatch Calibration Technique.
IEICE Transactions 91-A(9): 2465-2474 (2008) |
| 2007 |
|---|
| 3 | EE | Jingbo Duan,
Fule Li,
Liyuan Liu,
Dongmei Li,
Yongming Li,
Zhihua Wang:
A Pipelined A/D Conversion Technique with Low INL and DNL.
ISCAS 2007: 3391-3394 |
| 2 | EE | Fule Li,
Zhihua Wang,
Dongmei Li:
An Incomplete Settling Technique for Pipelined Analog-to-Digital Converters.
ISCAS 2007: 3590-3593 |
| 2006 |
|---|
| 1 | EE | Shuaiqi Wang,
Fule Li,
Yasuaki Inoue:
A 15-bit 10-Msample/s Pipelined A/D Converter Based on Incomplete Settling Principle.
IEICE Transactions 89-A(10): 2732-2739 (2006) |
