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Horst A. Gieser

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2006
7EEM. Etherton, N. Qu, J. Willemen, Wolfgang Wilkening, S. Mettler, M. Dissegna, R. Stella, L. Zullino, A. Andreini, Horst A. Gieser: Study of CDM specific effects for a smart power input protection structure. Microelectronics Reliability 46(5-6): 666-676 (2006)
6EEHeinrich Wolf, Horst A. Gieser, Detlef Bonfert, Markus Hauser: ESD Susceptibility of Submicron Air Gaps. Microelectronics Reliability 46(9-11): 1587-1590 (2006)
5EEDetlef Bonfert, Horst A. Gieser, Heinrich Wolf, M. Frank, A. Konrad, J. Schulz: Transient-induced latch-up test setup for wafer-level and package-level. Microelectronics Reliability 46(9-11): 1629-1633 (2006)
2005
4EEHeinrich Wolf, Horst A. Gieser, Wolfgang Stadler, Wolfgang Wilkening: Capacitively coupled transmission line pulsing cc-TLP--a traceable and reproducible stress method in the CDM-domain. Microelectronics Reliability 45(2): 279-285 (2005)
3EES. Bargstädt-Franke, Wolfgang Stadler, K. Esmark, M. Streibl, K. Domanski, Horst A. Gieser, Heinrich Wolf, W. Bala: Transient latch-up: experimental analysis and device simulation. Microelectronics Reliability 45(2): 297-304 (2005)
2EEHeinrich Wolf, Horst A. Gieser, Wolfgang Soldner, Harald Gossner: A Dedicated TLP Set-Up to Investigate the ESD Robustness of RF Elements and Circuits. Microelectronics Reliability 45(9-11): 1421-1424 (2005)
2003
1EEHorst A. Gieser: On-chip electrostatic discharge ESD. Microelectronics Reliability 43(7): 985-986 (2003)

Coauthor Index

1A. Andreini [7]
2W. Bala [3]
3S. Bargstädt-Franke [3]
4Detlef Bonfert [5] [6]
5M. Dissegna [7]
6K. Domanski [3]
7K. Esmark [3]
8M. Etherton [7]
9M. Frank [5]
10Harald Gossner [2]
11Markus Hauser [6]
12A. Konrad [5]
13S. Mettler [7]
14N. Qu [7]
15J. Schulz [5]
16Wolfgang Soldner [2]
17Wolfgang Stadler [3] [4]
18R. Stella [7]
19M. Streibl [3]
20Wolfgang Wilkening [4] [7]
21J. Willemen [7]
22Heinrich Wolf [2] [3] [4] [5] [6]
23L. Zullino [7]

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)