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Ganesan Umanesan

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2005
4EEGanesan Umanesan, Eiji Fujiwara: Parallel Decoding Cyclic Burst Error Correcting Codes. IEEE Trans. Computers 54(1): 87-92 (2005)
2003
3EEGanesan Umanesan, Eiji Fujiwara: A Class of Random Multiple Bits in a Byte Error Correcting and Single Byte Error Detecting (S_t/b EC-S_bED) Codes. IEEE Trans. Computers 52(7): 835-847 (2003)
2002
2EEGanesan Umanesan, Eiji Fujiwara: A Class of Random Multiple Bits in a Byte Error Correcting (S t/b EC)Codes for Semiconductor Memory Systems. PRDC 2002: 247-256
2000
1EEGanesan Umanesan, Eiji Fujiwara: Single Byte Error Control Codes with Double Bit within a Block Error Correcting Capability for Semiconductor Memory Systems. DFT 2000: 192-200

Coauthor Index

1Eiji Fujiwara [1] [2] [3] [4]

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)