| 2008 |
|---|
| 16 | EE | Moritoshi Yasunaga,
Yoshiki Yamaguchi,
Hiroshi Nakayama,
Ikuo Yoshihara,
Naoki Koizumi,
Jung Hwan Kim:
The Segmental-Transmission-Line: Its Design and Prototype Evaluation.
ICES 2008: 130-140 |
| 2007 |
|---|
| 15 | EE | Yoshiki Yamaguchi,
Noriyuki Aibe,
Moritoshi Yasunaga,
Yorihisa Yamamoto,
Takaaki Awano,
Ikuo Yoshihara:
Bio-Inspired Functional Asymmetry Camera System.
ICONIP (2) 2007: 637-646 |
| 14 | EE | Hung Dinh Nguyen,
Ikuo Yoshihara,
Kunihito Yamamori,
Moritoshi Yasunaga:
Implementation of an Effective Hybrid GA for Large-Scale Traveling Salesman Problems.
IEEE Transactions on Systems, Man, and Cybernetics, Part B 37(1): 92-99 (2007) |
| 13 | EE | Hung Dinh Nguyen,
Ikuo Yoshihara,
Kunihito Yamamori,
Moritoshi Yasunaga:
A New Three-Level Tree Data Structure for Representing TSP Tours in the Lin-Kernighan Heuristic.
IEICE Transactions 90-A(10): 2187-2193 (2007) |
| 2005 |
|---|
| 12 | EE | Naoki Koizumi,
Ikuo Yoshihara,
Kunihito Yamamori,
Moritoshi Yasunaga:
Variable length segmental-transmission-line and its parameter optimization based on GA.
Congress on Evolutionary Computation 2005: 1576-1582 |
| 2003 |
|---|
| 11 | EE | Moritoshi Yasunaga,
Ikuo Yoshihara,
Jung Hwan Kim:
Gene Finding Using Evolvable Reasoning Hardware.
ICES 2003: 198-207 |
| 2002 |
|---|
| 10 | EE | Kin'ya Takahashi,
Kunihito Yamamori,
Ikuo Yoshihara,
Susumu Horiguchi:
Comparison with Defect Compensation Methods for Feed-forward Neural Networks.
PRDC 2002: 293-300 |
| 2001 |
|---|
| 9 | | Moritoshi Yasunaga,
Jung Hwan Kim,
Ikuo Yoshihara:
Evolvable Reasoning Hardware: Its Prototyping and Performance Evaluation.
Genetic Programming and Evolvable Machines 2(3): 211-230 (2001) |
| 2000 |
|---|
| 8 | EE | Moritoshi Yasunaga,
Ikuo Yoshihara,
Jung Hwan Kim:
A High Speed and High Fault Tolerant Reconfigurable Reasoning System: Toward a Wafer Scale Reconfigurable Reasoning LSI.
DFT 2000: 69-77 |
| 7 | EE | Moritoshi Yasunaga,
Taro Nakamura,
Jung Hwan Kim,
Ikuo Yoshihara:
Kernel-Based Pattern Recognition Hardware: Its Design Methodology Using Evolved Truth Tables.
Evolvable Hardware 2000: 253-262 |
| 6 | EE | Moritoshi Yasunaga,
Jung Hwan Kim,
Ikuo Yoshihara:
The application of genetic algorithms to the design of reconfigurable reasoning VLSI chips.
FPGA 2000: 116-125 |
| 5 | | Michael Yasunaga,
Taro Nakamura,
Ikuo Yoshihara,
Jung Hwan Kim:
Kernel Optimization in Pattern Recognition Using a Genetic Algorithm.
GECCO 2000: 391 |
| 4 | | Ikuo Yoshihara,
Tomoo Aoyama,
Moritoshi Yasunaga:
A Fast Model-Building Method for Time Series Using Genetic Programming.
GECCO 2000: 537 |
| 3 | EE | Moritoshi Yasunaga,
Taro Nakamura,
Ikuo Yoshihara,
Jung Hwan Kim:
Genetic Algorithm-Based Methodology for Pattern Recognition Hardware.
ICES 2000: 264-273 |
| 2 | EE | Tomoo Aoyama,
Hanxi Zhu,
Ikuo Yoshihara:
Forecasting of the Chaos by Iterations Including Multi-Layer Neural-Network.
IJCNN (4) 2000: 467-471 |
| 1997 |
|---|
| 1 | | Ikuo Yoshihara:
Book Review: Genetic Programming IV.
Artificial Life 3(4): 335-336 (1997) |
