| 2007 |
|---|
| 6 | EE | Hao San,
Yoshitaka Jingu,
Hiroki Wada,
Hiroyuki Hagiwara,
Akira Hayakawa,
Haruo Kobayashi,
Tatsuji Matsuura,
Kouichi Yahagi,
Junya Kudoh,
Hideo Nakane,
Masao Hotta,
Toshiro Tsukada,
Koichiro Mashiko,
Atsushi Wada:
A Second-Order Multibit Complex Bandpass DeltaSigmaAD Modulator with I, Q Dynamic Matching and DWA Algorithm.
IEICE Transactions 90-C(6): 1181-1188 (2007) |
| 2006 |
|---|
| 5 | EE | Hao San,
Akira Hayakawa,
Yoshitaka Jingu,
Hiroki Wada,
Hiroyuki Hagiwara,
Kazuyuki Kobayashi,
Haruo Kobayashi,
Tatsuji Matsuura,
Kouichi Yahagi,
Junya Kudoh,
Hideo Nakane,
Masao Hotta,
Toshiro Tsukada,
Koichiro Mashiko,
Atsushi Wada:
Complex Bandpass DeltaSigmaAD Modulator Architecture without I, Q-Path Crossing Layout.
IEICE Transactions 89-A(4): 908-915 (2006) |
| 4 | EE | Masafumi Uemori,
Haruo Kobayashi,
Tomonari Ichikawa,
Atsushi Wada,
Koichiro Mashiko,
Toshiro Tsukada,
Masao Hotta:
High-Speed Continuous-Time Subsampling Bandpass DeltaSigmaAD Modulator Architecture Employing Radio Frequency DAC.
IEICE Transactions 89-A(4): 916-923 (2006) |
| 1997 |
|---|
| 3 | | Hiroaki Suzuki,
Hiroshi Makino,
Koichiro Mashiko,
Hisanori Hamano:
A Floating Point Divider using Redundant Binary Circuits and an Asynchronous Clock Scheme.
ICCD 1997: 685-689 |
| 1996 |
|---|
| 2 | EE | Koichiro Mashiko:
How to design low-power digital cellular phones.
ISLPED 1996: 177-180 |
| 1985 |
|---|
| 1 | | Hiroshi Miyamoto,
Koichiro Mashiko,
Yoshikazu Morooka,
Kazutami Arimoto,
Michihiro Yamada,
T. Nakano:
Test Pattern Considerations for Fault Tolerant High Density DRAM.
ITC 1985: 451-455 |
