2008 |
12 | EE | Hao San,
Hajime Konagaya,
Feng Xu,
Atsushi Motozawa,
Haruo Kobayashi,
Kazumasa Ando,
Hiroshi Yoshida,
Chieto Murayama,
Kanichi Miyazawa:
Novel Architecture of Feedforward Second-Order Multibit Delta-Sigma-AD Modulator.
IEICE Transactions 91-A(4): 965-970 (2008) |
2007 |
11 | EE | Hao San,
Yoshitaka Jingu,
Hiroki Wada,
Hiroyuki Hagiwara,
Akira Hayakawa,
Haruo Kobayashi,
Masao Hotta:
A 2.8-V Multibit Complex Bandpass Delta-Sigma-AD Modulator in 0.18µm CMOS.
ASP-DAC 2007: 96-97 |
10 | EE | Hao San,
Yoshitaka Jingu,
Hiroki Wada,
Hiroyuki Hagiwara,
Akira Hayakawa,
Haruo Kobayashi,
Tatsuji Matsuura,
Kouichi Yahagi,
Junya Kudoh,
Hideo Nakane,
Masao Hotta,
Toshiro Tsukada,
Koichiro Mashiko,
Atsushi Wada:
A Second-Order Multibit Complex Bandpass DeltaSigmaAD Modulator with I, Q Dynamic Matching and DWA Algorithm.
IEICE Transactions 90-C(6): 1181-1188 (2007) |
2006 |
9 | EE | Takanori Komuro,
Naoto Hayasaka,
Haruo Kobayashi,
Hiroshi Sakayori:
A Practical Analog BIST Cooperated with an LSI Tester.
IEICE Transactions 89-A(2): 465-468 (2006) |
8 | EE | Hao San,
Akira Hayakawa,
Yoshitaka Jingu,
Hiroki Wada,
Hiroyuki Hagiwara,
Kazuyuki Kobayashi,
Haruo Kobayashi,
Tatsuji Matsuura,
Kouichi Yahagi,
Junya Kudoh,
Hideo Nakane,
Masao Hotta,
Toshiro Tsukada,
Koichiro Mashiko,
Atsushi Wada:
Complex Bandpass DeltaSigmaAD Modulator Architecture without I, Q-Path Crossing Layout.
IEICE Transactions 89-A(4): 908-915 (2006) |
7 | EE | Masafumi Uemori,
Haruo Kobayashi,
Tomonari Ichikawa,
Atsushi Wada,
Koichiro Mashiko,
Toshiro Tsukada,
Masao Hotta:
High-Speed Continuous-Time Subsampling Bandpass DeltaSigmaAD Modulator Architecture Employing Radio Frequency DAC.
IEICE Transactions 89-A(4): 916-923 (2006) |
2005 |
6 | EE | Takanori Komuro,
Naoto Hayasaka,
Haruo Kobayashi,
Hiroshi Sakayori:
A practical BIST circuit for analog portion in deep sub-micron CMOS system LSI.
ISCAS (5) 2005: 4281-4284 |
5 | EE | Jun Otsuki,
Hao San,
Haruo Kobayashi,
Takanori Komuro,
Yoshihisa Yamada,
Aiyan Liu:
Reducing Spurious Output of Balanced Modulators by Dynamic Matching of I, Q Quadrature Paths.
IEICE Transactions 88-C(6): 1290-1294 (2005) |
2004 |
4 | EE | Hao San,
Haruo Kobayashi,
Shinya Kawakami,
Nobuyuki Kuroiwa:
An Element Rotation Algorithm for Multi-bit DAC Nonlinearities in Complex Bandpass \Delta\SigmaAD Modulators.
VLSI Design 2004: 151-156 |
1995 |
3 | | Haruo Kobayashi,
Hiroshi Sakayori,
Tsutomu Tobari,
Hiroyuki Matsuura:
Error Correction Algorithm for Folding/Interpolation ADC.
ISCAS 1995: 700-703 |
2 | EE | Haruo Kobayashi,
Takashi Matsumoto,
Tetsuya Yagi,
Koji Tanaka:
Light-adaptive architectures for regularization vision chips.
Neural Networks 8(1): 87-101 (1995) |
1993 |
1 | EE | Haruo Kobayashi,
Takashi Matsumoto,
Tetsuya Yagi,
Takuji Shimmi:
Image processing regularization filters on layered architecture.
Neural Networks 6(3): 327-350 (1993) |