| |
| 2000 | ||
|---|---|---|
| 1 | EE | Hirofumi Sakamoto, Ken'ichiro Uda, Bu-Y. Lee, Hiroyuki Ochi, Kazuo Taki, Takao Tsuda: A 16-bit redundant binary multiplier using low-power pass-transistor logic SPL. ASP-DAC 2000: 33-34 |
| 1 | Bu-Y. Lee | [1] |
| 2 | Hiroyuki Ochi | [1] |
| 3 | Hirofumi Sakamoto | [1] |
| 4 | Kazuo Taki | [1] |
| 5 | Takao Tsuda | [1] |