| 2008 |
|---|
| 7 | EE | Hiroaki Suzuki,
Masanori Kurimoto,
Tadao Yamanaka,
Hidehiro Takata,
Hiroshi Makino,
Hirofumi Shinohara:
Post-silicon programmed body-biasing platform suppressing device variability in 45 nm CMOS technology.
ISLPED 2008: 15-20 |
| 2005 |
|---|
| 6 | | Yasumasa Tsukamoto,
Koji Nii,
Susumu Imaoka,
Yuji Oda,
Shigeki Ohbayashi,
Tomoaki Yoshizawa,
Hiroshi Makino,
Koichiro Ishibashi,
Hirofumi Shinohara:
Worst-case analysis to obtain stable read/write DC margin of high density 6T-SRAM-array with local Vth variability.
ICCAD 2005: 398-405 |
| 5 | EE | Niichi Itoh,
Yasumasa Tsukamoto,
Takeshi Shibagaki,
Koji Nii,
Hidehiro Takata,
Hiroshi Makino:
A 32×24-bit multiplier-accumulator with advanced rectangular styled Wallace-tree structure.
ISCAS (1) 2005: 73-76 |
| 1998 |
|---|
| 4 | EE | Koji Nii,
Hiroshi Makino,
Yoshiki Tujihashi,
Chikayoshi Morishima,
Yasushi Hayakawa,
Hiroyuki Nunogami,
Takahiko Arakawa,
Hisanori Hamano:
A low power SRAM using auto-backgate-controlled MT-CMOS.
ISLPED 1998: 293-298 |
| 1997 |
|---|
| 3 | | Hiroaki Suzuki,
Hiroshi Makino,
Koichiro Mashiko,
Hisanori Hamano:
A Floating Point Divider using Redundant Binary Circuits and an Asynchronous Clock Scheme.
ICCD 1997: 685-689 |
| 1993 |
|---|
| 2 | | Hiroshi Makino,
Yasunobu Nakase,
Hirofumi Shinohara:
A 8.8-ns 54 54-Bit Multiplier Using New Redundant Binary Architecture.
ICCD 1993: 202-205 |
| 1980 |
|---|
| 1 | EE | Hiroshi Makino,
Makoto Kizawa:
An Automatic Translation System Of Non-Segmented Kana Sentences Into Kanji-Kana Sentences.
COLING 1980: 295-302 |
