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Masanori Yamato

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2005
6 Yoshiyasu Ogasawara, Norito Kato, Masanori Yamato, Mikiko Sato, Koichi Sasada, Kaname Uchikura, Mitaro Namiki, Hironori Nakajo: A New Model of Reconfigurable Cache for an SMT Processor and its FPGA Implementation. PDPTA 2005: 447-453
5 Kaname Uchikura, Koichi Sasada, Mikiko Sato, Masanori Yamato, Norito Kato, Hironori Nakajo, Mitaro Namiki: Development of a Thread Scheduler for SMT Processor Architecture. PDPTA 2005: 454-460
2004
4 Norito Kato, Masanori Yamato, Osamu Tujimoto, Mikiko Sato, Koichi Sasada, Kaname Uchikura, Mitaro Namiki, Hironori Nakajo: Dynamic Allocation of Physical Register Banks for an SMT Processor. PDPTA 2004: 317-323
2003
3 Mikiko Sato, Koichi Sasada, Shoji Kawahara, Norito Kato, Masanori Yamato, Hironori Nakajo, Mitaro Namiki: A Process and Thread Management of the Operating System "Future" for On Chip Multithreaded Architecture. PDPTA 2003: 1669-1675
2 Hironori Nakajo, Masanori Yamato, Shoji Kawahara, Norito Kato, Koichi Sasada, Mikiko Sato, Mitaro Namiki: Performance Evaluation of an On-Chip Multi-Threaded Processor with Cache Memory Managed by Logical Thread Number. PDPTA 2003: 1775-1781
1 Koichi Sasada, Mikiko Sato, Shoji Kawahara, Norito Kato, Masanori Yamato, Hironori Nakajo, Mitaro Namiki: Implementation and Evaluation of a Thread Library for Multithreaded Architecture. PDPTA 2003: 609-615

Coauthor Index

1Norito Kato [1] [2] [3] [4] [5] [6]
2Shoji Kawahara [1] [2] [3]
3Hironori Nakajo [1] [2] [3] [4] [5] [6]
4Mitaro Namiki [1] [2] [3] [4] [5] [6]
5Yoshiyasu Ogasawara [6]
6Koichi Sasada [1] [2] [3] [4] [5] [6]
7Mikiko Sato [1] [2] [3] [4] [5] [6]
8Osamu Tujimoto [4]
9Kaname Uchikura [4] [5] [6]

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)