2008 |
30 | | Shinobu Miwa,
Hironori Ichibayashi,
Hidetsugu Irie,
Masahiro Goshima,
Hironori Nakajo,
Shinji Tomita:
Low-Complexity Bypass Network Using Small RAM.
CDES 2008: 153-159 |
29 | EE | Noboru Tanabe,
Hironori Nakajo:
An Enhancer of Memory and Network for Cluster and its Applications.
PDCAT 2008: 99-106 |
28 | EE | Noboru Tanabe,
Hironori Nakajo:
Introduction to Acceleration for MPI Derived Datatypes Using an Enhancer of Memory and Network.
PVM/MPI 2008: 324-325 |
2007 |
27 | | Atushi Ohta,
Yoshihiro Hamada,
Akira Kitamura,
Noboru Tanabe,
Hideharu Amano,
Hironori Nakajo:
Implementation and Evaluation of Multicast Mechanism on Network Interface Plugged into a Memory Slot.
PDPTA 2007: 787-793 |
26 | | Satoshi Watanabe,
Yoshiyasu Ogasawara,
Ippei Tate,
Hirofumi Yano,
Hironori Nakajo:
Toward Parallel and Distributed Processing on High-Density Network with Mobile Devices.
PDPTA 2007: 794-800 |
25 | | Akira Kitamura,
Yasuo Miyabe,
Tomotaka Miyashiro,
Noboru Tanabe,
Hironori Nakajo,
Hideharu Amano:
Performance evaluation on low-latency communication mechanism of DIMMnet-2.
Parallel and Distributed Computing and Networks 2007: 57-62 |
2006 |
24 | EE | Tomotaka Miyashiro,
Akira Kitamura,
Hironori Nakajo,
Noboru Tanabe:
DIMMnet-2: A Reconfigurable Board Connected Into a Memory Slot.
FPL 2006: 1-4 |
23 | | Jun Kanai,
Takuro Mori,
Takeshi Araki,
Noboru Tanabe,
Hironori Nakajo,
Mitaro Namiki:
Implementation of PC Cluster System with Memory Mapped File by Commodity OS.
PDPTA 2006: 902-908 |
22 | | Ippei Tate,
Yoshiyasu Ogasawara,
Mikiko Sato,
Koichi Sasada,
Kaname Uchikura,
Kazunari Asano,
Satoshi Watanabe,
Mitaro Namiki,
Hironori Nakajo:
A Model of Implementable SMT Processor on FPGA.
PDPTA 2006: 909-915 |
21 | | Yoshiyasu Ogasawara,
Ippei Tate,
Satoshi Watanabe,
Mikiko Sato,
Koichi Sasada,
Kaname Uchikura,
Kazunari Asano,
Mitaro Namiki,
Hironori Nakajo:
Towards Reconfigurable Cache Memory for a Multithreaded Processor.
PDPTA 2006: 916-924 |
2005 |
20 | EE | Akira Kitamura,
Yasuo Miyabe,
Tetsu Izawa,
Tomotaka Miyashiro,
Konosuke Watanabe,
Tomohiro Otsuka,
Hideharu Amano,
Yoshihiro Hamada,
Noboru Tanabe,
Hironori Nakajo:
Evaluation of Network Interface Controller on DIMMnet-2 Prototype Board.
PDCAT 2005: 778-780 |
19 | | Yoshiyasu Ogasawara,
Norito Kato,
Masanori Yamato,
Mikiko Sato,
Koichi Sasada,
Kaname Uchikura,
Mitaro Namiki,
Hironori Nakajo:
A New Model of Reconfigurable Cache for an SMT Processor and its FPGA Implementation.
PDPTA 2005: 447-453 |
18 | | Kaname Uchikura,
Koichi Sasada,
Mikiko Sato,
Masanori Yamato,
Norito Kato,
Hironori Nakajo,
Mitaro Namiki:
Development of a Thread Scheduler for SMT Processor Architecture.
PDPTA 2005: 454-460 |
17 | | Yoshihiro Hamada,
Hiroaki Nishi,
Akira Kitamura,
Noboru Tanabe,
Hideharu Amano,
Hironori Nakajo:
A Packet Forwarding Layer for DIMMnet and its Hardware Implementation.
PDPTA 2005: 461-467 |
2004 |
16 | EE | Noboru Tanabe,
Hironori Nakajo,
Hirotaka Hakozaki,
Masasige Nakatake,
Yasunori Dohi,
Hideharu Amano:
A New Memory Module for Memory Intensive Applications.
PARELEC 2004: 123-128 |
15 | | Norito Kato,
Masanori Yamato,
Osamu Tujimoto,
Mikiko Sato,
Koichi Sasada,
Kaname Uchikura,
Mitaro Namiki,
Hironori Nakajo:
Dynamic Allocation of Physical Register Banks for an SMT Processor.
PDPTA 2004: 317-323 |
2003 |
14 | | Mikiko Sato,
Koichi Sasada,
Shoji Kawahara,
Norito Kato,
Masanori Yamato,
Hironori Nakajo,
Mitaro Namiki:
A Process and Thread Management of the Operating System "Future" for On Chip Multithreaded Architecture.
PDPTA 2003: 1669-1675 |
13 | | Hironori Nakajo,
Masanori Yamato,
Shoji Kawahara,
Norito Kato,
Koichi Sasada,
Mikiko Sato,
Mitaro Namiki:
Performance Evaluation of an On-Chip Multi-Threaded Processor with Cache Memory Managed by Logical Thread Number.
PDPTA 2003: 1775-1781 |
12 | | Koichi Sasada,
Mikiko Sato,
Shoji Kawahara,
Norito Kato,
Masanori Yamato,
Hironori Nakajo,
Mitaro Namiki:
Implementation and Evaluation of a Thread Library for Multithreaded Architecture.
PDPTA 2003: 609-615 |
2002 |
11 | EE | Noboru Tanabe,
Yoshihiro Hamada,
Hironori Nakajo,
Hideki Imashiro,
Junji Yamamoto,
Tomohiro Kudoh,
Hideharu Amano:
Low Latency Communication on DIMMnet-1 Network Interface Plugged into a DIMM Slot.
PARELEC 2002: 9-14 |
10 | | Noboru Tanabe,
Junji Yamamoto,
Hiroaki Nishi,
Tomohiro Kudoh,
Yoshihiro Hamada,
Hironori Nakajo,
Hideharu Amano:
Low Latency High Bandwidth Message Transfer Mechanisms for a Network Interface Plugged into a Memory Slot.
Cluster Computing 5(1): 7-17 (2002) |
2000 |
9 | EE | Noboru Tanabe,
Junji Yamamoto,
Hiroaki Nishi,
Tomohiro Kudoh,
Yoshihiro Hamada,
Hironori Nakajo,
Hideharu Amano:
MEMOnet : Network interface plugged into a memory slot.
CLUSTER 2000: 17-16 |
8 | EE | Noboru Tanabe,
Junji Yamamoto,
Hiroaki Nishi,
Tomohiro Kudoh,
Yoshihiro Hamada,
Hironori Nakajo,
Hideharu Amano:
On-the-fly Sending: A Low Latency High Bandwidth Message Transfer Mechanism.
ISPAN 2000: 186-194 |
7 | | Hironori Nakajo,
M. Ishii,
T. Kudo,
Hideharu Amano:
Coherence Protocol for Home Proxy Cache on RHiNET.
PDPTA 2000 |
6 | | Hironori Nakajo,
Akihiro Ichikawa,
Yukio Kaneda:
A Distributed Shared-Memory System on a Workstation Cluster Using Fast Serial Links.
International Journal of Parallel Programming 28(2): 179-194 (2000) |
1998 |
5 | | Hironori Nakajo,
Hidekazu Tanaka,
Yoshinori Nakanishi,
Masaki Kohata,
Yukio Kaneda:
Distributed Shared-Memory for a Workstation Cluster with a High Speed Serial Interface.
HPCN Europe 1998: 588-597 |
1997 |
4 | | Hironori Nakajo,
Akihiro Ichikawa,
Yukio Kaneda:
An Implementation and Evaluation of a Distributed Shared-Memory System on Workstation Clusters Using Fast Serial Links.
ISHPC 1997: 143-158 |
3 | EE | Hironori Nakajo,
Satoshi Ohtani,
Takashi Matsumoto,
Masadi Kohata,
Kei Hiraki,
Yukio Kaneda:
An I/O Network Architecture of the Distributed Shared-Memory Massively Parallel Computer JUMP-1.
International Conference on Supercomputing 1997: 253-260 |
1996 |
2 | | Hironori Nakajo,
Satoshi Ohtani,
Yukio Kaneda:
A Simulation-based Evaluation of a Disk I/O Subsystem for a Massively Parallel Computer: JUMP-1.
ICDCS 1996: 562-569 |
1995 |
1 | | Hironori Nakajo,
Takashi Matsumoto,
Masaki Kohata,
Hideo Matsuda,
Kei Hiraki,
Yukio Kaneda:
High Performance I/O System of the Distributed Shared-Memory Massively Parallel Computer JUMP-1.
Parallel and Distributed Computing and Systems 1995: 470-473 |