| 2009 |
|---|
| 10 | EE | José Manuel Velasco,
David Atienza,
Katzalin Olcoz:
Exploration of memory hierarchy configurations for efficient garbage collection on high-performance embedded systems.
ACM Great Lakes Symposium on VLSI 2009: 3-8 |
| 2007 |
|---|
| 9 | | José Manuel Velasco,
David Atienza,
Katzalin Olcoz,
Francisco Tirado:
Efficient Object Placement including Node Selection in a Distributed Virtual Machine.
PARCO 2007: 509-516 |
| 2005 |
|---|
| 8 | | José Manuel Velasco,
David Atienza,
Katzalin Olcoz,
Francky Catthoor:
Performance Evaluation of Barrier Techniques for Distributed Tracing Garbage Collectors.
PARCO 2005: 549-556 |
| 7 | EE | José Manuel Velasco,
David Atienza,
Katzalin Olcoz,
Francky Catthoor,
Francisco Tirado,
Jose Manuel Mendias:
Energy Characterization of Garbage Collectors for Dynamic Applications on Embedded Systems.
PATMOS 2005: 69-78 |
| 2004 |
|---|
| 6 | EE | José Manuel Velasco,
Katzalin Olcoz,
Francisco Tirado:
Adaptive Tuning of Reserved Space in an Appel Collector.
ECOOP 2004: 543-559 |
| 5 | EE | José Manuel Velasco,
David Atienza,
Francky Catthoor,
Francisco Tirado,
Katzalin Olcoz,
Jose Manuel Mendias:
Garbage Collector Refinement for New Dynamic Multimedia Applications on Embedded Systems.
Interaction between Compilers and Computer Architectures 2004: 25-32 |
| 4 | EE | José Manuel Velasco,
Antonio Ortiz,
Katzalin Olcoz,
Francisco Tirado:
Dynamic Management of Nursery Space Organization in Generational Collection.
Interaction between Compilers and Computer Architectures 2004: 33-40 |
| 1999 |
|---|
| 3 | EE | Katzalin Olcoz,
Francisco Tirado,
Hortensia Mecha:
Unified data path allocation and BIST intrusion.
Integration 28(1): 55-99 (1999) |
| 1998 |
|---|
| 2 | EE | Katzalin Olcoz,
Francisco Tirado:
Register Allocation with Simultaneous BIST Intrusio.
EUROMICRO 1998: 10099-10106 |
| 1996 |
|---|
| 1 | EE | Hortensia Mecha,
Milagros Fernández,
Francisco Tirado,
Julio Septién,
D. Motes,
Katzalin Olcoz:
A method for area estimation of data-path in high level synthesis.
IEEE Trans. on CAD of Integrated Circuits and Systems 15(2): 258-265 (1996) |
