1999 | ||
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1 | EE | Pak K. Chan, Mark J. Boyd, S. Goren, K. Klenk, V. Kodavati, R. Kundu, M. Margolese, J. Sun, K. Suzuki, E. Thorne, X. Wang, J. Xu, M. Zhu: Reducing Compilation Time of Zhong's FPGA-Based SAT Solver. FCCM 1999: 308-309 |
1 | Mark J. Boyd | [1] |
2 | Pak K. Chan | [1] |
3 | S. Goren | [1] |
4 | K. Klenk | [1] |
5 | V. Kodavati | [1] |
6 | R. Kundu | [1] |
7 | M. Margolese | [1] |
8 | J. Sun | [1] |
9 | K. Suzuki | [1] |
10 | X. Wang | [1] |
11 | J. Xu | [1] |
12 | M. Zhu | [1] |