Ben A. Abderazek

2009
18	EE	Arquimedes Canedo, Ben A. Abderazek, Masahiro Sowa: Compiler Support for Code Size Reduction Using a Queue-Based Processor. T. HiPEAC 2: 269-285 (2009)
2008
17	EE	Arquimedes Canedo, Masahiro Sowa, Ben A. Abderazek: Quantitative Evaluation of Common Subexpression Elimination on Queue Machines. ISPAN 2008: 25-30
16	EE	Ben A. Abderazek, Arquimedes Canedo, Tsutomu Yoshinaga, Masahiro Sowa: The QC-2 parallel Queue processor architecture. J. Parallel Distrib. Comput. 68(2): 235-245 (2008)
15	EE	Md. Musfiquzzaman Akanda, Ben A. Abderazek, Masahiro Sowa: Dual-execution mode processor architecture. The Journal of Supercomputing 44(2): 103-125 (2008)
2007
14	EE	Arquimedes Canedo, Ben A. Abderazek, Masahiro Sowa: An Efficient Code Generation Algorithm for Code Size Reduction Using 1-Offset P-Code Queue Computation Model. EUC 2007: 196-208
13	EE	Ben A. Abderazek, Mushfiquzzaman Akanda, Tsutomu Yoshinaga, Masahiro Sowa: Mathematical Model for Multiobjective Synthesis of NoC Architectures. ICPP Workshops 2007: 36
12	EE	Arquimedes Canedo, Ben A. Abderazek, Masahiro Sowa: New Code Generation Algorithm for QueueCore—An Embedded Processor with High ILP. PDCAT 2007: 185-192
11	EE	Arquimedes Canedo, Ben A. Abderazek, Masahiro Sowa: Queue Register File Optimization Algorithm for QueueCore Processor. SBAC-PAD 2007: 169-176
10	EE	Yuki Nakanishi, Arquimedes Canedo, Ben A. Abderazek, Masahiro Sowa: Optimizing Reaching Definitions Overhead in Queue Processors. JCIT 2(4): 36-40 (2007)
2006
9	EE	Ben A. Abderazek, Tsutomu Yoshinaga, Masahiro Sowa: Scalable Core-Based Methodology and Synthesizable Core for Systematic Design. ICPP Workshops 2006: 345-352
8	EE	Md. Musfiquzzaman Akanda, Ben A. Abderazek, Masahiro Sowa: On the Design of a Dual-Execution Modes Processor: Architecture and Preliminary Evaluation. ISPA Workshops 2006: 37-46
7	EE	Ben A. Abderazek, Sotaro Kawata, Masahiro Sowa: Design and architecture for an embedded 32-bit QueueCore. J. Embedded Computing 2(2): 191-205 (2006)
6	EE	Ben A. Abderazek, Tsutomu Yoshinaga, Masahiro Sowa: High-Level Modeling and FPGA Prototyping of Produced Order Parallel Queue Processor Core. The Journal of Supercomputing 38(1): 3-15 (2006)
2005
5	EE	Ben A. Abderazek, Sotaro Kawata, Tsutomu Yoshinaga, Masahiro Sowa: Modular Design Structure and High-Level Prototyping for Novel Embedded Processor Core. EUC 2005: 340-349
4	EE	Md. Musfiquzzaman Akanda, Ben A. Abderazek, Sotaro Kawata, Masahiro Sowa: An Efficient Dynamic Switching Mechanism (DSM) for Hybrid Processor Architecture. EUC 2005: 77-86
3	EE	Masahiro Sowa, Ben A. Abderazek, Tsutomu Yoshinaga: Parallel Queue Processor Architecture Based on Produced Order Computation Model. The Journal of Supercomputing 32(3): 217-229 (2005)
2003
2	EE	Ben A. Abderazek, Soichi Shigeta, Tsutomu Yoshinaga, Masahiro Sowa: On the Design of a Register Queue Based Processor Architecture (FaRM-rq). ISPA 2003: 248-262
2002
1		Masahiro Sowa, Ben A. Abderazek, Soichi Shigeta, Kirilka Nikolova, Tsutomu Yoshinaga: Proposal and Design of a Parallel Queue Processor Architecture (PQP). IASTED PDCS 2002: 549-554

Coauthor Index

1	Md. Musfiquzzaman Akanda	[4] [8] [15]
2	Mushfiquzzaman Akanda	[13]
3	Arquimedes Canedo	[10] [11] [12] [14] [16] [17] [18]
4	Sotaro Kawata	[4] [5] [7]
5	Yuki Nakanishi	[10]
6	Kirilka Nikolova	[1]
7	Soichi Shigeta	[1] [2]
8	Masahiro Sowa	[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18]
9	Tsutomu Yoshinaga	[1] [2] [3] [5] [6] [9] [13] [16]