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Soichi Shigeta

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2006
4EESoichi Shigeta, Nobutaka Imamura, Haruyasu Ueda, Hiromichi Kobashi, Miho Murata, Taketoshi Yoshida, Atsushi Kubota, Akira Asato, Yoshimasa Kadooka: Grid Service Platform: Design and Implementation of Grid Middleware for Telecom Carriers. e-Science 2006: 110
2003
3EEBen A. Abderazek, Soichi Shigeta, Tsutomu Yoshinaga, Masahiro Sowa: On the Design of a Register Queue Based Processor Architecture (FaRM-rq). ISPA 2003: 248-262
2002
2 Masahiro Sowa, Ben A. Abderazek, Soichi Shigeta, Kirilka Nikolova, Tsutomu Yoshinaga: Proposal and Design of a Parallel Queue Processor Architecture (PQP). IASTED PDCS 2002: 549-554
2001
1 Soichi Shigeta, Kentaro Shimizu, Masahiro Sowa: Access route control by an extended key/lock scheme. Comput. Syst. Sci. Eng. 16(5): 319-325 (2001)

Coauthor Index

1Ben A. Abderazek [2] [3]
2Akira Asato [4]
3Nobutaka Imamura [4]
4Yoshimasa Kadooka [4]
5Hiromichi Kobashi [4]
6Atsushi Kubota [4]
7Miho Murata [4]
8Kirilka Nikolova [2]
9Kentaro Shimizu [1]
10Masahiro Sowa [1] [2] [3]
11Haruyasu Ueda [4]
12Taketoshi Yoshida [4]
13Tsutomu Yoshinaga [2] [3]

Colors in the list of coauthors

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)