| |
| 1989 | ||
|---|---|---|
| 5 | EE | Kuang-Wei Chiang: Resistance Extraction and Resistance Calculation in GOALIE? DAC 1989: 682-685 |
| 4 | EE | Kuang-Wei Chiang, Surendra Nahar, Chi-Yuan Lo: Time-efficient VLSI artwork analysis algorithms in GOALIE2. IEEE Trans. on CAD of Integrated Circuits and Systems 8(6): 640-648 (1989) |
| 1988 | ||
| 3 | EE | Kuang-Wei Chiang, Surendra Nahar, Chi-Yuan Lo: Time Efficient VLSI Artwork Analysis Algorithms in GOALIE2. DAC 1988: 471-475 |
| 1984 | ||
| 2 | Kuang-Wei Chiang, Zvonko G. Vranesic: Comments on ``Fault Diagnosis of MOS Combinational Networks''. IEEE Trans. Computers 33(10): 947 (1984) | |
| 1983 | ||
| 1 | Kuang-Wei Chiang, Zvonko G. Vranesic: A Tree Representation of Combinational Networks. IEEE Trans. Computers 32(3): 315-319 (1983) | |
| 1 | Chi-Yuan Lo | [3] [4] |
| 2 | Surendra Nahar | [3] [4] |
| 3 | Zvonko G. Vranesic | [1] [2] |