| |
| 2006 | ||
|---|---|---|
| 2 | EE | Koh Johguchi, Zhaomin Zhu, Hans Jürgen Mattausch, Tetsushi Koide, Tetsuo Hironaka, Kazuya Tanigawa: Unified Data/Instruction Cache with Hierarchical Multi-Port Architecture and Hidden Precharge Pipeline. APCCAS 2006: 1297-1300 |
| 2005 | ||
| 1 | EE | Takashi Morimoto, Osamu Kiriyama, Hidekazu Adachi, Zhaomin Zhu, Tetsushi Koide, Hans Jürgen Mattausch: A low-power video segmentation LSI with boundary-active-only architecture. ASP-DAC 2005: 13-14 |
| 1 | Hidekazu Adachi | [1] |
| 2 | Tetsuo Hironaka | [2] |
| 3 | Koh Johguchi | [2] |
| 4 | Osamu Kiriyama | [1] |
| 5 | Tetsushi Koide | [1] [2] |
| 6 | Hans Jürgen Mattausch | [1] [2] |
| 7 | Takashi Morimoto | [1] |
| 8 | Kazuya Tanigawa | [2] |