| |
| 2006 | ||
|---|---|---|
| 2 | EE | Lesley Shannon, Blair Fort, Samir Parikh, Arun Patel, Manuel Saldaña, Paul Chow: A System Design Methodology for Reducing System Integration Time and Facilitating Modular Design Verification. FPL 2006: 1-6 |
| 2005 | ||
| 1 | Lesley Shannon, Blair Fort, Samir Parikh, Arun Patel, Manuel Saldaña, Paul Chow: Designing an FPGA SoC Using a Standardized IP Block Interface. FPT 2005: 341-342 | |
| 1 | Paul Chow | [1] [2] |
| 2 | Blair Fort | [1] [2] |
| 3 | Arun Patel | [1] [2] |
| 4 | Manuel Saldaña | [1] [2] |
| 5 | Lesley Shannon | [1] [2] |