| |
| 2008 | ||
|---|---|---|
| 6 | Tomi Metsälä, Tomi Westerlund, Seppo Virtanen, Juha Plosila: Rigorous Communication Modelling at Transaction Level With Systemc. ICSOFT (SE/MUSE/GSDCA) 2008: 246-251 | |
| 5 | EE | Johanna Tuominen, Tomi Westerlund, Juha Plosila: Power Aware System Refinement. Electr. Notes Theor. Comput. Sci. 201: 223-253 (2008) |
| 2007 | ||
| 4 | EE | Tomi Westerlund, Juha Plosila: Time Aware System Refinement. Electr. Notes Theor. Comput. Sci. 187: 91-106 (2007) |
| 2006 | ||
| 3 | EE | Tomi Westerlund, Juha Plosila: Time Aware Modelling and Analysis of Multiclocked VLSI Systems. ICFEM 2006: 737-756 |
| 2005 | ||
| 2 | EE | Tomi Westerlund, Juha Plosila: Formal Specification of a Protocol Processor. SAMOS 2005: 122-131 |
| 2004 | ||
| 1 | EE | Tiberiu Seceleanu, Tomi Westerlund: Aspects of Formal and Graphical Design of a Bus System. DATE 2004: 396-403 |
| 1 | Tomi Metsälä | [6] |
| 2 | Juha Plosila | [2] [3] [4] [5] [6] |
| 3 | Tiberiu Seceleanu | [1] |
| 4 | Johanna Tuominen | [5] |
| 5 | Seppo Virtanen | [6] |