| |
| 2008 | ||
|---|---|---|
| 2 | EE | Shi-Hao Chen, Jiing-Yuan Lin: Experiences of low power design implementation and verification. ASP-DAC 2008: 742-747 |
| 2007 | ||
| 1 | EE | Shi-Hao Chen, Ke-Cheng Chu, Jiing-Yuan Lin, Cheng-Hong Tsai: DFM/DFY practices during physical designs for timing, signal integrity, and power. ASP-DAC 2007: 232-237 |
| 1 | Ke-Cheng Chu | [1] |
| 2 | Jiing-Yuan Lin | [1] [2] |
| 3 | Cheng-Hong Tsai | [1] |