| 2009 |
|---|
| 47 | EE | Chris R. Jesshope,
Mike Lankamp,
Li Zhang:
Evaluating CMPs and Their Memory Architecture.
ARCS 2009: 246-257 |
| 2008 |
|---|
| 46 | EE | Thuy Duong Vu,
Li Zhang,
Chris R. Jesshope:
The Verification of the On-Chip COMA Cache Coherence Protocol.
AMAST 2008: 413-429 |
| 45 | EE | Chris R. Jesshope:
Building a Concurrency and Resource Allocation Model into a Processor's ISA.
Euro-Par Workshops 2008: 129-130 |
| 44 | EE | Chris R. Jesshope:
Introduction to Programming Multicores.
SAMOS 2008: 207 |
| 43 | EE | Chris R. Jesshope,
Jean-Marc Philippe,
Michiel van Tol:
An Architecture and Protocol for the Management of Resources in Ubiquitous and Heterogeneous Systems Based on the SVP Model of Concurrency.
SAMOS 2008: 218-228 |
| 42 | EE | Chris R. Jesshope:
Operating Systems in silicon and the Dynamic Management of Resources in Many-Core Chips.
Parallel Processing Letters 18(2): 257-274 (2008) |
| 2007 |
|---|
| 41 | | Keqiu Li,
Chris R. Jesshope,
Hai Jin,
Jean-Luc Gaudiot:
Network and Parallel Computing, IFIP International Conference, NPC 2007, Dalian, China, September 18-21, 2007, Proceedings
Springer 2007 |
| 40 | EE | Nabil Hasasneh,
Ian Bell,
Chris R. Jesshope:
High Level Modelling and Design For a Microthreaded Scheduler to Support Microgrids.
AICCSA 2007: 301-308 |
| 39 | EE | Li Zhang,
Chris R. Jesshope:
On-Chip COMA Cache-Coherence Protocol for Microgrids of Microthreaded Cores.
Euro-Par Workshops 2007: 38-48 |
| 38 | EE | Thuy Duong Vu,
Chris R. Jesshope:
Formalizing SANE Virtual Processor in Thread Algebra.
ICFEM 2007: 345-365 |
| 37 | EE | Thomas A. M. Bernard,
Chris R. Jesshope,
Peter M. W. Knijnenburg:
Strategies for Compiling µ TC to Novel Chip Multiprocessors.
SAMOS 2007: 127-138 |
| 36 | EE | Nabil Hasasneh,
Ian Bell,
Chris R. Jesshope:
Asynchronous arbiter for micro-threaded chip multiprocessors.
Journal of Systems Architecture 53(5-6): 253-262 (2007) |
| 2006 |
|---|
| 35 | | Chris R. Jesshope,
Colin Egan:
Advances in Computer Systems Architecture, 11th Asia-Pacific Conference, ACSAC 2006, Shanghai, China, September 6-8, 2006, Proceedings
Springer 2006 |
| 34 | EE | Nabil Hasasneh,
Ian Bell,
Chris R. Jesshope:
Scalable and Partitionable Asynchronous Arbiter for Micro-threaded Chip Multiprocessors.
ARCS 2006: 252-267 |
| 33 | EE | Chris R. Jesshope:
muTC - An Intermediate Language for Programming Chip Multiprocessors.
Asia-Pacific Computer Systems Architecture Conference 2006: 147-160 |
| 32 | EE | Kostas Bousias,
Nabil Hasasneh,
Chris R. Jesshope:
Instruction Level Parallelism through Microthreading - A Scalable Approach to Chip Multiprocessors.
Comput. J. 49(2): 211-233 (2006) |
| 31 | EE | Chris R. Jesshope,
Alexander V. Shafarenko:
Special issue on Micro-grids - Guest Editor Introduction.
International Journal of Parallel Programming 34(3): 189-192 (2006) |
| 30 | EE | Chris R. Jesshope,
Alexander V. Shafarenko:
Guest Editor's Introduction (Part 2).
International Journal of Parallel Programming 34(4): 319-322 (2006) |
| 29 | EE | Ian Bell,
Nabil Hasasneh,
Chris R. Jesshope:
Supporting Microthread Scheduling and Synchronisation in CMPs.
International Journal of Parallel Programming 34(4): 343-381 (2006) |
| 28 | EE | Chris R. Jesshope:
Microthreading a Model for Distributed Instruction-level Concurrency.
Parallel Processing Letters 16(2): 209-228 (2006) |
| 2005 |
|---|
| 27 | EE | Kostas Bousias,
Chris R. Jesshope:
The Challenges of Massive On-Chip Concurrency.
Asia-Pacific Computer Systems Architecture Conference 2005: 157-170 |
| 2004 |
|---|
| 26 | | Lipeng Wen,
Chris R. Jesshope:
A General Learning Management System Based on Schema-driven Methodology.
ICALT 2004 |
| 25 | EE | Chris R. Jesshope:
Scalable Instruction-Level Parallelism..
SAMOS 2004: 383-392 |
| 2003 |
|---|
| 24 | EE | Chris R. Jesshope:
Multi-threaded Microprocessors - Evolution or Revolution.
Asia-Pacific Computer Systems Architecture Conference 2003: 21-45 |
| 23 | | Lipeng Wen,
Chris R. Jesshope:
Web Services Technology and Learning Technology- A Web-Services Model for Constructing Decentralized Virtual Learning Environments.
ICWS 2003: 507-514 |
| 2001 |
|---|
| 22 | EE | Chris R. Jesshope:
Implementing an efficient vector instruction set in a chip multi-processor using micro-threaded pipelines.
ACSAC 2001: 80-88 |
| 21 | EE | Ramón Beivide,
Chris R. Jesshope,
Antonio Robles,
Cruz Izu:
Topic 12: Routing and Communication in Interconnection Networks.
Euro-Par 2001: 611-612 |
| 20 | | Regina Gehne,
Chris R. Jesshope,
Zhenzi Zhang:
Technology Integrated Learning Environment - A Web-based Distance Learning System.
IMSA 2001: 1-6 |
| 19 | EE | Hong Hong,
Neena Albi,
Kinshuk,
Xiaoqin He,
Ashok Patel,
Chris R. Jesshope:
Adaptivity in Web-based Educational System.
WWW Posters 2001 |
| 18 | EE | Chris R. Jesshope:
Cost-Effective Multimedia in On-line Teaching.
Educational Technology & Society 4(3): (2001) |
| 2000 |
|---|
| 17 | EE | Chris R. Jesshope,
Bing Luo:
Micro-Threading: A New Approach to Future RISC.
ACAC 2000: 34-41 |
| 1999 |
|---|
| 16 | EE | Chris R. Jesshope:
Parallel Computer Architecture - What Is Its Future? Introduction.
Euro-Par 1999: 695-697 |
| 15 | EE | Chris R. Jesshope:
Computers as Tutors: Solving the Crisis in Education.
Educational Technology & Society 2(4): (1999) |
| 1998 |
|---|
| 14 | EE | Murray Pearson,
Chris R. Jesshope:
Multi-campus teaching using computer networks.
ACSE 1998: 106-111 |
| 1997 |
|---|
| 13 | EE | Chris R. Jesshope:
Web based teaching: a minimalist approach.
ACSE 1997: 16-23 |
| 12 | | Julian A. B. Dines,
John F. Snowdon,
Marc P. Y. Desmulliez,
Dima B. Barsky,
Alexander V. Shafarenko,
Chris R. Jesshope:
Optical Interconnectivity in a Scalable Data-Parallel System.
J. Parallel Distrib. Comput. 41(1): 120-130 (1997) |
| 1996 |
|---|
| 11 | | Julian A. B. Dines,
John F. Snowdon,
Marc P. Y. Desmulliez,
D. T. Nielson,
Dima B. Barsky,
Alexander V. Shafarenko,
Chris R. Jesshope:
Optical Interconnection hardware for scalable systems.
PDPTA 1996: 367-374 |
| 1994 |
|---|
| 10 | | Chris R. Jesshope,
Vesselin Jossifov,
Wolfgang Wilhelmi:
Parcella 1994, VI. International Workshop on Parallel Processing by Cellular Automata and Arrays, Potsdam, September 21-23, 1994. Proceedings
Akademie Verlag, Berlin 1994 |
| 1993 |
|---|
| 9 | | Chris R. Jesshope,
Cruz Izu:
The MP1 Network Chip and its Application to Parallel Computers.
Comput. J. 36(8): 763-777 (1993) |
| 8 | | Chris R. Jesshope:
Latency Reduction in VLSI Routers.
Parallel Processing Letters 3: 485-494 (1993) |
| 1991 |
|---|
| 7 | | Vladimir Getov,
Chris R. Jesshope:
Simulation Facility of Distributed Memory System with "Mad Postman" Communication Network.
EDMCC 1991: 224-233 |
| 1989 |
|---|
| 6 | EE | Chris R. Jesshope,
P. R. Miller,
Jay T. Yantchev:
High Performance Communications in Processor Networks.
ISCA 1989: 150-157 |
| 1988 |
|---|
| 5 | | Chris R. Jesshope,
Philip Miller,
Jelio Yantchev:
Programming with active data.
Parcella 1988: 111-129 |
| 4 | | Chris R. Jesshope:
Transputers and switches as objects in OCCAM.
Parallel Computing 8(1-3): 19-30 (1988) |
| 1985 |
|---|
| 3 | | Chris R. Jesshope,
M. J. Crawley,
G. L. Lovegrove:
An Intelligent Pascal Editor for a Graphical Oriented Workstation.
Softw., Pract. Exper. 15(11): 1103-1119 (1985) |
| 1980 |
|---|
| 2 | | Chris R. Jesshope:
The Implementation of Fast Radix 2 Transforms on Array Processors.
IEEE Trans. Computers 29(1): 20-27 (1980) |
| 1 | | Chris R. Jesshope:
Some Results Concerning Data Routing in Array Processors.
IEEE Trans. Computers 29(7): 659-662 (1980) |
