Jia-Lang Lin

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1997

1 EE An-Nan Suen, Jhing-Fa Wang, Jia-Lang Lin: VLSI architecture and implementation for FS1016 CELP decoder with reduced power and memory requirements. Integration 24(1): 79-97 (1997)

1997
1	EE	An-Nan Suen, Jhing-Fa Wang, Jia-Lang Lin: VLSI architecture and implementation for FS1016 CELP decoder with reduced power and memory requirements. Integration 24(1): 79-97 (1997)

Coauthor Index

1 An-Nan Suen [1]

2 Jhing-Fa Wang [1]